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    <title>S32K中的主题 Re: Internal clocking requirements</title>
    <link>https://community.nxp.com/t5/S32K/Internal-clocking-requirements/m-p/838104#M3320</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chun,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I recommend you&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;to take&lt;/SPAN&gt;&amp;nbsp;a look at the reference manual in section&amp;nbsp;&lt;STRONG&gt;28.2 Introduction&lt;SPAN style="font-size: 11.0pt;"&gt;, &lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;RM rev.9.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The S32K has three run modes:&lt;/P&gt;&lt;P&gt;RUN, HSRUN&amp;nbsp;and VLPR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, we will select RUN mode, because is the normal operating mode for the device out of reset.&lt;/P&gt;&lt;P&gt;In this mode, SYS_CLK can be configured up to max 80 MHz.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All the related information can be found in section&amp;nbsp;&lt;STRONG&gt;27.4 Internal clocking requirements &lt;/STRONG&gt;and&amp;nbsp;&lt;STRONG&gt;Option 2: Normal RUN&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;There you can see the configuration&amp;nbsp;of registers where the SYS_CLK&amp;nbsp;is set to 80 MHz and BUS_CLK to 40 MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you want to reach 80 MHz you need to use PLL. You cannot use internal clock FIRC directly because it generates max 48 MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The SPLL can be sourced by the SOSC reference clock. That is why you need to&amp;nbsp;initialize SOSC clock, SPLL clock, and SCG reference clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can find the code made for the S32K144 you can find in the S32DS File-&amp;gt;S32DS Project from Example-&amp;gt;S32K144-&amp;gt;hello_clocks_s32k144.&lt;/P&gt;&lt;P&gt;The clock settings can be found in clocks_and_modes.c.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I believe it helps you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Diana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 06 Dec 2018 14:21:20 GMT</pubDate>
    <dc:creator>dianabatrlova</dc:creator>
    <dc:date>2018-12-06T14:21:20Z</dc:date>
    <item>
      <title>Internal clocking requirements</title>
      <link>https://community.nxp.com/t5/S32K/Internal-clocking-requirements/m-p/838103#M3319</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class="" data-section="0" style="color: #333333; background-color: #f7f8fa; font-weight: normal; font-size: 14px;"&gt;&lt;SPAN class="" data-group="0-0" data-section="0" data-sentence="0"&gt;hi&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-section="1" style="color: #333333; background-color: #f7f8fa; font-weight: normal; font-size: 14px;"&gt;&lt;SPAN class="" data-group="1-0" data-section="1" data-sentence="0" style="color: #4a90e2;"&gt;I use the S32K chip, the introduction of which says that 80Mhz frequency can be used. Now I look at the clock tree of the chip, I do not know how to select the external crystal oscillator. Can I only select the internal clock if I want to use 80Mhz frequency?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-section="2" style="color: #333333; background-color: #f7f8fa; font-weight: normal; font-size: 14px;"&gt;&lt;SPAN class="" data-group="2-0" data-section="2" data-sentence="0"&gt;Sorry my English is not good, all the above is translated.&lt;/SPAN&gt;&lt;SPAN class="" data-group="2-1" data-section="2" data-sentence="1"&gt;Forgive me&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Dec 2018 09:33:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Internal-clocking-requirements/m-p/838103#M3319</guid>
      <dc:creator>c_han</dc:creator>
      <dc:date>2018-12-05T09:33:01Z</dc:date>
    </item>
    <item>
      <title>Re: Internal clocking requirements</title>
      <link>https://community.nxp.com/t5/S32K/Internal-clocking-requirements/m-p/838104#M3320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chun,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I recommend you&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;to take&lt;/SPAN&gt;&amp;nbsp;a look at the reference manual in section&amp;nbsp;&lt;STRONG&gt;28.2 Introduction&lt;SPAN style="font-size: 11.0pt;"&gt;, &lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;RM rev.9.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The S32K has three run modes:&lt;/P&gt;&lt;P&gt;RUN, HSRUN&amp;nbsp;and VLPR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, we will select RUN mode, because is the normal operating mode for the device out of reset.&lt;/P&gt;&lt;P&gt;In this mode, SYS_CLK can be configured up to max 80 MHz.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All the related information can be found in section&amp;nbsp;&lt;STRONG&gt;27.4 Internal clocking requirements &lt;/STRONG&gt;and&amp;nbsp;&lt;STRONG&gt;Option 2: Normal RUN&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;There you can see the configuration&amp;nbsp;of registers where the SYS_CLK&amp;nbsp;is set to 80 MHz and BUS_CLK to 40 MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you want to reach 80 MHz you need to use PLL. You cannot use internal clock FIRC directly because it generates max 48 MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The SPLL can be sourced by the SOSC reference clock. That is why you need to&amp;nbsp;initialize SOSC clock, SPLL clock, and SCG reference clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can find the code made for the S32K144 you can find in the S32DS File-&amp;gt;S32DS Project from Example-&amp;gt;S32K144-&amp;gt;hello_clocks_s32k144.&lt;/P&gt;&lt;P&gt;The clock settings can be found in clocks_and_modes.c.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I believe it helps you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Diana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Dec 2018 14:21:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Internal-clocking-requirements/m-p/838104#M3320</guid>
      <dc:creator>dianabatrlova</dc:creator>
      <dc:date>2018-12-06T14:21:20Z</dc:date>
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