https://community.nxp.com/t5/S32K/Clock-FIRC-amp-PLL-settings/m-p/1831499#M33195 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/227246">@Dev15</a>&nbsp;</P> <P>As you select FIRC as the clock source you need to disable the PLL as mentioned in the warning. the warning would not be a problem.&nbsp;</P> <P>&nbsp;</P> <P>B.R.</P> <P>VaneB</P> Tue, 19 Mar 2024 23:24:01 GMT VaneB 2024-03-19T23:24:01Z https://community.nxp.com/t5/S32K/Clock-FIRC-amp-PLL-settings/m-p/1831308#M33182 <P>Hi Team,</P><P>I'm using RTD 3.0.0, S32K312, SDK 3.5 version and trying to configure PWM channels. The core clock is set to FIRC and could see a warning.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Dev15_0-1710865361390.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/269279iF6C5DF70A4241D8B/image-size/medium?v=v2&amp;px=400" role="button" title="Dev15_0-1710865361390.png" alt="Dev15_0-1710865361390.png" /></span></P><P>&nbsp;</P><P>Please help to resolve it.</P><P>Thank you</P><P>&nbsp;</P> Tue, 19 Mar 2024 16:23:03 GMT https://community.nxp.com/t5/S32K/Clock-FIRC-amp-PLL-settings/m-p/1831308#M33182 Dev15 2024-03-19T16:23:03Z https://community.nxp.com/t5/S32K/Clock-FIRC-amp-PLL-settings/m-p/1831499#M33195 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/227246">@Dev15</a>&nbsp;</P> <P>As you select FIRC as the clock source you need to disable the PLL as mentioned in the warning. the warning would not be a problem.&nbsp;</P> <P>&nbsp;</P> <P>B.R.</P> <P>VaneB</P> Tue, 19 Mar 2024 23:24:01 GMT https://community.nxp.com/t5/S32K/Clock-FIRC-amp-PLL-settings/m-p/1831499#M33195 VaneB 2024-03-19T23:24:01Z