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    <title>topic ADC1 Legacy Code Upgrade - Need More Channels Enabled in S32K</title>
    <link>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1831319#M33183</link>
    <description>&lt;P&gt;I'm sure I'm missing something simple, but I'm working with a bit of code I didn't configure for the K144 MCU that is being used on a new PCBA. The existing code reads four channels on ADC1, so SC0:SC3, [SE7, SE6, SE10, SE11] are configured. This code works fine.&lt;/P&gt;&lt;P&gt;I now need to enable two more channels SE12 and SE13, but I can't seem to figure out the initialization of the configuration. I am not sure that I have the channels properly connected to the pins and then turned-on to sample.&lt;BR /&gt;&lt;BR /&gt;Here is the code that works for four channels.&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;____&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#if&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ENABLE_ADC1_INIT&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /******************************************************&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* Initialize ADC1:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* ADC1_SE7, ADC1_SE6, ADC1_SE10, ADC1_SE11, [ADC1_SE12, ADC1_SE13: Are these properly configured?]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* hardware trigger,&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* single conversion, 12-bit resolution&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;******************************************************/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;PCC&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;PCCn&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;PCC_ADC1_INDEX&lt;/SPAN&gt;&lt;SPAN&gt;] |= (&lt;/SPAN&gt;&lt;SPAN&gt;PCC_PCCn_PCS&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;) | &lt;/SPAN&gt;&lt;SPAN&gt;PCC_PCCn_CGC_MASK&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* PCS = 3: Select FIRCDIV2 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* CGC = 1: Enable bus clock in ADC1 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;SPAN&gt;#if&lt;/SPAN&gt; &lt;SPAN&gt;ENABLE_ADC_CALIBRATION&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;// Mandatory calibration&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLPS&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP0&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP1&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP2&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP3&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP9&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLPX&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC3&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;= &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_CAL_MASK&lt;/SPAN&gt;&lt;SPAN&gt; | &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_AVGE_MASK&lt;/SPAN&gt;&lt;SPAN&gt; | &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_AVGS&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;while&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;0UL&lt;/SPAN&gt;&lt;SPAN&gt; == ((&lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;] &amp;amp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_COCO_MASK&lt;/SPAN&gt;&lt;SPAN&gt;) &amp;gt;&amp;gt; &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_COCO_SHIFT&lt;/SPAN&gt;&lt;SPAN&gt;))&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* Wait for completion of calibration */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#endif&lt;/SPAN&gt;&lt;SPAN&gt; // ENABLE_ADC_CALIBRATION&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CFG1&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_CFG1_MODE&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; /* MODE = 1: 12-bit conversion */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC2&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;= &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC2_ADTRG_MASK&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;SPAN&gt; /* ADTRG = 1: HW trigger */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC3&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* ADCO = 0: One conversion performed */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* AVGE,AVGS = 0: HW average function disabled */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;// Enable module for conversions&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;7&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;// ADC1_SE7 selected for ADC1_SC1A&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;6&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;// ADC1_SE6 selected for ADC1_SC1B&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE10 selected for ADC1_SC1C&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;11&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE11 selected for ADC1_SC1D&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;12&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE12 selected for ADC1_SC1E //my new line&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;13&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE13 selected for ADC1_SC1F //my new line&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#endif&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; // ENABLE_ADC1_INIT&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;______&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN&gt;The two new channels [//my new line(s)] read '0' counts when I loading them with these lines:&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;hardware_ad_pid1_counts&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;R&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;hardware_ad_pid2_counts&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;R&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;If I assign ADC1-&amp;gt;SC1[1] = ADC_SC1_ADCH(12);, then I can get the expected PTA15 reading on ADC1-&amp;gt;R[1] so it seems to not be sampling the two added channels.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I have seen a reference that SC1[0]:[3] are handled differently, but I haven't been able to figure out what I need to add/fix to my code to get ADC readings from pins PTA15 &amp;amp; PTA16 turned on.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Can anybody suggest a fix?&lt;BR /&gt;&lt;BR /&gt;Thanks in advance.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Tue, 19 Mar 2024 16:52:20 GMT</pubDate>
    <dc:creator>Tim_Z</dc:creator>
    <dc:date>2024-03-19T16:52:20Z</dc:date>
    <item>
      <title>ADC1 Legacy Code Upgrade - Need More Channels Enabled</title>
      <link>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1831319#M33183</link>
      <description>&lt;P&gt;I'm sure I'm missing something simple, but I'm working with a bit of code I didn't configure for the K144 MCU that is being used on a new PCBA. The existing code reads four channels on ADC1, so SC0:SC3, [SE7, SE6, SE10, SE11] are configured. This code works fine.&lt;/P&gt;&lt;P&gt;I now need to enable two more channels SE12 and SE13, but I can't seem to figure out the initialization of the configuration. I am not sure that I have the channels properly connected to the pins and then turned-on to sample.&lt;BR /&gt;&lt;BR /&gt;Here is the code that works for four channels.&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;____&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#if&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ENABLE_ADC1_INIT&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /******************************************************&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* Initialize ADC1:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* ADC1_SE7, ADC1_SE6, ADC1_SE10, ADC1_SE11, [ADC1_SE12, ADC1_SE13: Are these properly configured?]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* hardware trigger,&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;* single conversion, 12-bit resolution&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;******************************************************/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;PCC&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;PCCn&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;PCC_ADC1_INDEX&lt;/SPAN&gt;&lt;SPAN&gt;] |= (&lt;/SPAN&gt;&lt;SPAN&gt;PCC_PCCn_PCS&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;) | &lt;/SPAN&gt;&lt;SPAN&gt;PCC_PCCn_CGC_MASK&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* PCS = 3: Select FIRCDIV2 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* CGC = 1: Enable bus clock in ADC1 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;SPAN&gt;#if&lt;/SPAN&gt; &lt;SPAN&gt;ENABLE_ADC_CALIBRATION&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;// Mandatory calibration&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLPS&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP0&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP1&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP2&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP3&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLP9&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CLPX&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC3&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;= &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_CAL_MASK&lt;/SPAN&gt;&lt;SPAN&gt; | &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_AVGE_MASK&lt;/SPAN&gt;&lt;SPAN&gt; | &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC3_AVGS&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;while&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;0UL&lt;/SPAN&gt;&lt;SPAN&gt; == ((&lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;] &amp;amp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_COCO_MASK&lt;/SPAN&gt;&lt;SPAN&gt;) &amp;gt;&amp;gt; &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_COCO_SHIFT&lt;/SPAN&gt;&lt;SPAN&gt;))&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* Wait for completion of calibration */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#endif&lt;/SPAN&gt;&lt;SPAN&gt; // ENABLE_ADC_CALIBRATION&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;CFG1&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_CFG1_MODE&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; /* MODE = 1: 12-bit conversion */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC2&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;= &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC2_ADTRG_MASK&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;SPAN&gt; /* ADTRG = 1: HW trigger */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC3&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0U&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* ADCO = 0: One conversion performed */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* AVGE,AVGS = 0: HW average function disabled */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;// Enable module for conversions&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;7&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;// ADC1_SE7 selected for ADC1_SC1A&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;6&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp;// ADC1_SE6 selected for ADC1_SC1B&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE10 selected for ADC1_SC1C&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;11&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE11 selected for ADC1_SC1D&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;12&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE12 selected for ADC1_SC1E //my new line&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;SC1&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;] = &lt;/SPAN&gt;&lt;SPAN&gt;ADC_SC1_ADCH&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;13&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;SPAN&gt; // ADC1_SE13 selected for ADC1_SC1F //my new line&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#endif&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; // ENABLE_ADC1_INIT&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;______&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN&gt;The two new channels [//my new line(s)] read '0' counts when I loading them with these lines:&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;hardware_ad_pid1_counts&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;R&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;hardware_ad_pid2_counts&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;ADC1&lt;/SPAN&gt;&lt;SPAN&gt;-&amp;gt;&lt;/SPAN&gt;&lt;SPAN&gt;R&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;If I assign ADC1-&amp;gt;SC1[1] = ADC_SC1_ADCH(12);, then I can get the expected PTA15 reading on ADC1-&amp;gt;R[1] so it seems to not be sampling the two added channels.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I have seen a reference that SC1[0]:[3] are handled differently, but I haven't been able to figure out what I need to add/fix to my code to get ADC readings from pins PTA15 &amp;amp; PTA16 turned on.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Can anybody suggest a fix?&lt;BR /&gt;&lt;BR /&gt;Thanks in advance.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 19 Mar 2024 16:52:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1831319#M33183</guid>
      <dc:creator>Tim_Z</dc:creator>
      <dc:date>2024-03-19T16:52:20Z</dc:date>
    </item>
    <item>
      <title>Re: ADC1 Legacy Code Upgrade - Need More Channels Enabled</title>
      <link>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1833659#M33347</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;
&lt;P&gt;According to your code: ADC1-&amp;gt;SC2 = ADC_SC2_ADTRG_MASK; /* &lt;STRONG&gt;ADTRG&lt;/STRONG&gt; = 1: HW trigger */&lt;BR /&gt;Hardware Trigger is used in your project.&lt;BR /&gt;Did you configure Hardware Trigger for those two new added channels?&lt;BR /&gt;Please read &lt;STRONG&gt;&lt;EM&gt;44.5.3 Hardware trigger and channel selects&lt;/EM&gt;&lt;/STRONG&gt; and of &lt;A href="https://www.nxp.com/webapp/Download?colCode=S32K1XXRM" target="_self"&gt;S32K1XXRM&lt;/A&gt; Rev14.1.&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;Figure 48-1 The ADC triggering scheme&lt;/EM&gt;&lt;/STRONG&gt; shows the &lt;STRONG&gt;ADHWTS&lt;/STRONG&gt; A:D of the first four channels SC1 [0]: [3] are different from others, please note that:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 48-1. ADC triggering scheme.png" style="width: 798px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/269953i2E18F026F29A04B2/image-size/large?v=v2&amp;amp;px=999" role="button" title="Figure 48-1. ADC triggering scheme.png" alt="Figure 48-1. ADC triggering scheme.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Fri, 22 Mar 2024 09:54:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1833659#M33347</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2024-03-22T09:54:01Z</dc:date>
    </item>
    <item>
      <title>Re: ADC1 Legacy Code Upgrade - Need More Channels Enabled</title>
      <link>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1833731#M33352</link>
      <description>&lt;P&gt;&amp;lt;&lt;SPAN&gt;Did you configure Hardware Trigger for those two new added channels?&amp;gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;No. I'm sure that this is the problem, but I cannot find an application note for configuring it for the new channels, five and six.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The new channels need to be read at startup but&amp;nbsp;differ from the first four channels that convert for the duration of the product's run time. The new channels could have a single conversion or could be part of the regular ADC1 conversions of the first four, and then be disabled, while the first four continue.&lt;BR /&gt;&lt;BR /&gt;Is there an example of setting channels (my 5 &amp;amp; 6) that are not part of the first four special channels that I can read?&lt;BR /&gt;&lt;BR /&gt;Tim&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Mar 2024 12:03:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1833731#M33352</guid>
      <dc:creator>Tim_Z</dc:creator>
      <dc:date>2024-03-22T12:03:44Z</dc:date>
    </item>
    <item>
      <title>Re: ADC1 Legacy Code Upgrade - Need More Channels Enabled</title>
      <link>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1836185#M33508</link>
      <description>&lt;P&gt;I don't know the specifics of your application, so you need to consider how to sample the remaining 2 ADC channels.&lt;BR /&gt;There are very few bare metal codes. It is recommended to refer to:&lt;BR /&gt;ADC Software Trigger examples in the &lt;A href="https://www.nxp.com/docs/en/application-note/AN5413.pdf" target="_self"&gt;AN5413 S32K1xx Series Cookbook&lt;/A&gt; and &lt;A href="https://www.nxp.com/webapp/Download?colCode=AN5413SW&amp;amp;docLang=en" target="_self"&gt;AN5413SW.zip&lt;/A&gt; for your reference.&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K144-PDB-ADC-trigger-DMA-ISR-S32DS/ta-p/1103221" target="_self"&gt;Example S32K144 PDB ADC trigger DMA ISR S32DS&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Mar 2024 08:58:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC1-Legacy-Code-Upgrade-Need-More-Channels-Enabled/m-p/1836185#M33508</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2024-03-27T08:58:32Z</dc:date>
    </item>
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