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    <title>S32KのトピックRe: s32k144 rtc problem on vlps mode</title>
    <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837541#M3313</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;thanks for your reply&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 04 Jul 2018 02:01:11 GMT</pubDate>
    <dc:creator>建宽高</dc:creator>
    <dc:date>2018-07-04T02:01:11Z</dc:date>
    <item>
      <title>s32k144 rtc problem on vlps mode</title>
      <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837537#M3309</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;hi,I want to know whether the internal real-time clock can run under VLPS mode?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;First, I checked the s32-rm (rev4) data&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="2" data-v-3c4f858a=""&gt;1. on P1367&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="3" data-v-3c4f858a=""&gt;Power, clocking, and reset&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="4" data-v-3c4f858a=""&gt;The RTC is an always powered-block that remains active in all low power modes&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="5" data-v-3c4f858a=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="6" data-v-3c4f858a=""&gt;That is, it works in all low power modes&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="6" data-v-3c4f858a=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="6" data-v-3c4f858a=""&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64657i4328E2A356DAAB55/image-size/large?v=v2&amp;amp;px=999" title="Snipaste_2018-07-02_14-10-35.jpg" alt="Snipaste_2018-07-02_14-10-35.jpg" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="7" data-v-3c4f858a=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="8" data-v-3c4f858a=""&gt;2. on P955&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="9" data-v-3c4f858a=""&gt;In powermanage, RTC in VLPS mode is off state,off Module and clock sources are disabled, and off represents the block clock source prohibition&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN data-group="9" data-v-3c4f858a=""&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64658iB2EEF0A8E28F3BFE/image-size/large?v=v2&amp;amp;px=999" title="Snipaste_2018-07-02_14-11-34.jpg" alt="Snipaste_2018-07-02_14-11-34.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64659i254B0BFE2E671A55/image-size/large?v=v2&amp;amp;px=999" title="Snipaste_2018-07-02_14-12-23.jpg" alt="Snipaste_2018-07-02_14-12-23.jpg" /&gt;&lt;/span&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;Therefore, I don't know whether RTC can work in VLPS mode, so I have done relevant experiments to prove whether VLPS continue to time from run-&amp;gt; lvps-&amp;gt; RUN ,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;Whether to continue timing in mode on vlps&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;/P&gt;&lt;P class="" data-v-3c4f858a=""&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;I have shown that both external crystal oscillations and internal real-time clocks within the internal clock source are valid&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 02 Jul 2018 06:19:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837537#M3309</guid>
      <dc:creator>建宽高</dc:creator>
      <dc:date>2018-07-02T06:19:30Z</dc:date>
    </item>
    <item>
      <title>Re: s32k144 rtc problem on vlps mode</title>
      <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837538#M3310</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Please use &lt;A href="https://www.nxp.com/docs/en/reference-manual/S32K-RM.pdf"&gt;S32K1xx_RM_r.7&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;The table has been updated.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64685i87EE4B71FC81DC93/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 02 Jul 2018 12:33:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837538#M3310</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2018-07-02T12:33:21Z</dc:date>
    </item>
    <item>
      <title>Re: s32k144 rtc problem on vlps mode</title>
      <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837539#M3311</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;thanks for your reply,I wonder what that means about Async operation ,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64724i268F3A740A1E4F45/image-size/large?v=v2&amp;amp;px=999" title="Snipaste_2018-07-03_09-16-41.jpg" alt="Snipaste_2018-07-03_09-16-41.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Jul 2018 01:16:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837539#M3311</guid>
      <dc:creator>建宽高</dc:creator>
      <dc:date>2018-07-03T01:16:43Z</dc:date>
    </item>
    <item>
      <title>Re: s32k144 rtc problem on vlps mode</title>
      <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837540#M3312</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Please refer to Table 7-8, S32K1xx_RM_r7.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/64811i29DDC443F50A3F49/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;All the other clock sources (LPOCLKS[RTCCLKSEL]) are gated off in VLPS.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Jul 2018 13:45:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837540#M3312</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2018-07-03T13:45:56Z</dc:date>
    </item>
    <item>
      <title>Re: s32k144 rtc problem on vlps mode</title>
      <link>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837541#M3313</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;thanks for your reply&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Jul 2018 02:01:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k144-rtc-problem-on-vlps-mode/m-p/837541#M3313</guid>
      <dc:creator>建宽高</dc:creator>
      <dc:date>2018-07-04T02:01:11Z</dc:date>
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