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    <title>S32K中的主题 STCU2 and FCC interactions</title>
    <link>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1813849#M31994</link>
    <description>&lt;P&gt;Hi There,&lt;/P&gt;&lt;P&gt;Reading User Manual i have understood that, please confirm or not (and, please, explain, if not):&lt;/P&gt;&lt;P&gt;1) Unrecoverable faults are configurable by the apposite ST32 studio Bist window (in peripherial view), isn't it?&lt;/P&gt;&lt;P&gt;3) Unrecoverable faults set&amp;nbsp; STRU2_ERR.UFSF bit&amp;nbsp; and a destructive reset reaction, isn't it?&lt;/P&gt;&lt;P&gt;4) Recoverable faults&amp;nbsp; set STRU2_ERR.RFSF and triggers one of FCCU NCF5 group of faults, Isn't it?&lt;/P&gt;&lt;P&gt;5) in user manual, in STCU2_ERR description, it is said&amp;nbsp; that also an unrecoverable fault, STRU2_ERR.UFSF=1, triggers FCCU, why? does it also triggers NCF5 group?&lt;/P&gt;&lt;P&gt;6) If SPD Bist_Run(BIST_SAFETYBOOT_CFG) is done prior to configure&amp;nbsp; FCCU, at init phases,&amp;nbsp;STRU2_ERR.RFSF is set but FCCU is not triggered, because it is not initializad yet, isn't it?&lt;/P&gt;&lt;P&gt;7) To validate&amp;nbsp;STRU2_ERR.RFSF path is it&amp;nbsp; necessary to inject in FCCU.NCFF one of the NCF5 fault numbers, for example, EMCEM_DCM_NCF_5_FAULT_MONITOR0 = 1, isnt'it ?&lt;/P&gt;&lt;P&gt;&lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt; if it is injected&amp;nbsp;EMCEM_DCM_NCF_5_FAULT_MONITOR0 = 1 in FCCU_NCFF is also set&amp;nbsp;STRU2_ERR.RFSF for testing it&amp;nbsp; ?&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Fabio&lt;/P&gt;</description>
    <pubDate>Thu, 22 Feb 2024 14:26:42 GMT</pubDate>
    <dc:creator>FabioG</dc:creator>
    <dc:date>2024-02-22T14:26:42Z</dc:date>
    <item>
      <title>STCU2 and FCC interactions</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1813849#M31994</link>
      <description>&lt;P&gt;Hi There,&lt;/P&gt;&lt;P&gt;Reading User Manual i have understood that, please confirm or not (and, please, explain, if not):&lt;/P&gt;&lt;P&gt;1) Unrecoverable faults are configurable by the apposite ST32 studio Bist window (in peripherial view), isn't it?&lt;/P&gt;&lt;P&gt;3) Unrecoverable faults set&amp;nbsp; STRU2_ERR.UFSF bit&amp;nbsp; and a destructive reset reaction, isn't it?&lt;/P&gt;&lt;P&gt;4) Recoverable faults&amp;nbsp; set STRU2_ERR.RFSF and triggers one of FCCU NCF5 group of faults, Isn't it?&lt;/P&gt;&lt;P&gt;5) in user manual, in STCU2_ERR description, it is said&amp;nbsp; that also an unrecoverable fault, STRU2_ERR.UFSF=1, triggers FCCU, why? does it also triggers NCF5 group?&lt;/P&gt;&lt;P&gt;6) If SPD Bist_Run(BIST_SAFETYBOOT_CFG) is done prior to configure&amp;nbsp; FCCU, at init phases,&amp;nbsp;STRU2_ERR.RFSF is set but FCCU is not triggered, because it is not initializad yet, isn't it?&lt;/P&gt;&lt;P&gt;7) To validate&amp;nbsp;STRU2_ERR.RFSF path is it&amp;nbsp; necessary to inject in FCCU.NCFF one of the NCF5 fault numbers, for example, EMCEM_DCM_NCF_5_FAULT_MONITOR0 = 1, isnt'it ?&lt;/P&gt;&lt;P&gt;&lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt; if it is injected&amp;nbsp;EMCEM_DCM_NCF_5_FAULT_MONITOR0 = 1 in FCCU_NCFF is also set&amp;nbsp;STRU2_ERR.RFSF for testing it&amp;nbsp; ?&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Fabio&lt;/P&gt;</description>
      <pubDate>Thu, 22 Feb 2024 14:26:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1813849#M31994</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-02-22T14:26:42Z</dc:date>
    </item>
    <item>
      <title>Re: STCU2 and FCC interactions</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1816864#M32179</link>
      <description>&lt;P&gt;Hi Fabio,&lt;BR /&gt;&lt;BR /&gt;ad 1)&lt;BR /&gt;Yes in the BIST configuration - Unrecoverable MBIST/LBIST tabs, you can set which LBIST/MBIST will be handled as unrecoverable.&lt;BR /&gt;&lt;BR /&gt;ad 3)&lt;BR /&gt;Yes correct.&lt;BR /&gt;&lt;BR /&gt;ad 4)&lt;BR /&gt;Yes, it sets the &lt;SPAN&gt;STCU2_ERR.RFSF&amp;nbsp;&lt;/SPAN&gt;flag and sets status flag for the NCF_5 channel – based on the NCF_5 channel setting it performs desired reaction.&lt;BR /&gt;&lt;BR /&gt;ad 5)&lt;BR /&gt;Unrecoverable STCU2 faults don't trigger FCCU, there is a note in the RM:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="radoslavbogusz_0-1709070564120.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/265374i4B7B00333F0CD022/image-size/large?v=v2&amp;amp;px=999" role="button" title="radoslavbogusz_0-1709070564120.png" alt="radoslavbogusz_0-1709070564120.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;BR /&gt;ad 6)&lt;BR /&gt;Correct, by default after the reset FCCU NCF channels are disabled.&lt;BR /&gt;If you want to utilize FCCU reporting path or EOUT signaling from STCU2 please execute eMcem_init() beforehand.&lt;BR /&gt;&lt;BR /&gt;ad 7)&lt;BR /&gt;STCU2 has no fault injection mechanism, you can only inject desired NCF_DCM fault ID and test the reaction path within FCCU.&lt;BR /&gt;ERRSTAT RFSF bit is not set when injecting fault into FCCU, this bit can’t be set by any fake injection.&lt;BR /&gt;STCU2 itself is mechanism to check latent faults in other peripherals or memories on the chip, checking latent faults in STCU2 (i.e. check latent faults in the HW STCU2 checker for checking other MCU latent faults) is beyond the scope of the metrics required by FuSa standards (that would lead to never-ending&amp;nbsp; chain of check of the checkers).&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Kind Regards,&lt;BR /&gt;Radoslav&lt;/P&gt;</description>
      <pubDate>Tue, 27 Feb 2024 22:01:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1816864#M32179</guid>
      <dc:creator>RadoslavB</dc:creator>
      <dc:date>2024-02-27T22:01:13Z</dc:date>
    </item>
    <item>
      <title>Re: STCU2 and FCC interactions</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1817418#M32249</link>
      <description>&lt;P&gt;At point 7 you say&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"STCU2 has no fault injection mechanism, you can only inject desired NCF_DCM fault ID and test the reaction path within FCCU."&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I suppose this is performed by a fake fault injection in FCCU.NCFF (correct)? so, How&amp;nbsp; can I check the "test rection path" you refer to ? How can I understand if the reaction path test result is correct, (after a FCCU.NCFF, NCF_DCM bit set)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Fabio&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 28 Feb 2024 10:24:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1817418#M32249</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-02-28T10:24:10Z</dc:date>
    </item>
    <item>
      <title>Re: STCU2 and FCC interactions</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1817505#M32260</link>
      <description>&lt;P&gt;Yes you can use&amp;nbsp; &lt;SPAN class="fontstyle0"&gt;eMcem_InjectFault() for fake fault injection into FCCU.&lt;BR /&gt;Reaction path can be tested by observing desired reaction:&lt;BR /&gt;- jump into Alarm interrupt handler (R1)&lt;BR /&gt;- jump into NMI (R1)&lt;BR /&gt;- triggering functional reset (R3)&lt;BR /&gt;- EOUT signaling in addition to R2 or R3&lt;BR /&gt;&lt;BR /&gt;You can also use sCheck FCCU_NCF check, this is available in Premium SAF.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Kind Regards,&lt;BR /&gt;Radoslav&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 28 Feb 2024 12:53:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-and-FCC-interactions/m-p/1817505#M32260</guid>
      <dc:creator>RadoslavB</dc:creator>
      <dc:date>2024-02-28T12:53:59Z</dc:date>
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