topic S32K312 - SPI Clock, MOSI make wrong pulse in S32K

S32K312 - SPI Clock, MOSI make wrong pulse

ssean — Mon, 19 Feb 2024 05:00:17 GMT

Hello.

When I send data to MOSI by called Spi_SyncTansmit(), SCK and MOSI make wrong pulse at start.

It happen only in use CPOL=1(Clock Idle HIGH, Active LOW).

If I set CPOL=0 (Clock Idle Low, Active HIGH), it is okay.

* RTD Version 2.0.1 (7, July, 2022)

1. Send 0x00 00

0x0000.jpeg

2. Send 0x07 31

0x0731.jpeg

3. LPSPI_1 Register value

LPSPI_1.jpeg

Best Regards,

Sean Sung

danielmartynek — Mon, 19 Feb 2024 13:06:07 GMT

It was discussed here:

The module is reset at the beginning of each transfer.

Normally, with your configuration OUTCFG = 0, the MOSI line should retains last value when chip select is negated (beetween transfers).

But the module is reset in the driver.

Regards,

Daniel

ssean — Tue, 20 Feb 2024 02:44:59 GMT

Thank you for reply.

It happen with OUTCFG=1, too.

Can you give me advise for how can I fix this problem?

Best Regards,

SEAN SUNG

danielmartynek — Tue, 20 Feb 2024 09:04:41 GMT

The issue is that the Lpspi_Ip_SyncTransmit() resets the LPSPI module in function Lpspi_TransmitTxInit().

You would need to remove the code that reset the LPSPI from the function.

Regards,

Daniel

ssean — Mon, 26 Feb 2024 08:36:29 GMT

I fix this issue to CS control by peripheral engine (not GPIO).

Thank you for reply.