topic Re: [S32K146] : Need help about ADC management in S32K

[S32K146] : Need help about ADC management

sebastien_ledio — Mon, 12 Nov 2018 08:03:30 GMT

Hello wonderful community,

I am working on S32K146 µc, and I try to "play" with ADC functionnality, but I occurs any understanding.

It is about SC1 (ADC Status and Control Register 1) and RA (ADC Data Result Registers).

These registers have each one 16 possible addresses. So I think basically than each address is for each ADC, I mean for ADC0 --> SC1[0] and RA[0], ADC1 --> SC1[1] and RA[1], ADC2 --> SC1[2] and RA[2], ..., ADC15 --> SC1[15] and RA[15]

But it seems unexact because ADCH from SC1 defines the channel used.

So I am a little lost, someone can help me to understand please.

Thanks by advance

Sebastien

Re: [S32K146] : Need help about ADC management

danielmartynek — Mon, 12 Nov 2018 15:41:01 GMT

Hello Sebastien,

The S32K146 derivative has 2 ADC instances, ADC0 and ADC1.

As you just described, if you use ADC0->SC1[0], regardless of ADCH which selects the analog inputs, the result will be in ADC0->R[0].

Regards,

Daniel

Re: [S32K146] : Need help about ADC management

sebastien_ledio — Mon, 12 Nov 2018 16:10:27 GMT

Hello Daniel,

thanks for your response, but in fact, in my understanding ADC0 means analog input 0 (channel 0), but not an instance, so know it is ok.

I have another question, on same instance (ADC0 for exemple), if there are 4 channels, is it possible to read in same time the ADC result of each analog input, and if yes how do you do this, because, if I correctly understand, you have to:

1 : Select your channel (one only), and initiate conversion

2 : Wait for ADC completion

3 : Read the ADC result (12 bits) on selected channel.

So with this exemple, it is not possible to read several channel in same time.

Thanks

Sebastien

Re: [S32K146] : Need help about ADC management

danielmartynek — Mon, 12 Nov 2018 20:15:16 GMT

Hello Sebastien,

The conversion can be trigger either by SW or by HW triggers.
However, only ADCn->SC1[0] support SW trigger and the conversion gets triggered by a write to SC1[0]_ADCH.
Once the conversion is done, SC1[0]_COCO bit is set and the data are available in ADC0->R[0].
The next conversion is again triggered by a write to SC1[0]_ADCH.

WH triggers are more flexible. PDB can be configured to trigger multiple channels in back-to-back conversion.
There is an example: https://community.nxp.com/docs/DOC-332749

Please note that the SDK ADC_PAL driver allows to trigger multiple channels by SW.

Regards,
Daniel