S32K中的主题 Re: Incorrect PWM frequency

Incorrect PWM frequency

vusal — Tue, 30 Jan 2024 23:32:12 GMT

Hello,

I am using PLL as my CORE_CLK at 160mHz. I have a PWM period of 10000. When I measure the PWM output, I am getting16.131kHz. I am not sure where 131Hz are coming from. Any thoughts? Thanks!

I have to write all bare-metal code for my project. This is the initialization code I followed:

Except SET(PLL_PLLODIV_DIV(2u)) which I had to set to 1u, otherwise I was getting 10.4kHz.

#define CLOCK_MODE_4_CONFIG \

(tCLOCK_CONFIG){ \

/* FLASH_CTL */ CLR(FLASH_CTL_RWSL_MASK)|SET(FLASH_CTL_RWSC(4u)), \

/* PRAMC0_PRCR1 */ CLR(PRAMC_PRCR1_P0_BO_DIS_MASK)|SET(PRAMC_PRCR1_FT_DIS_MASK), \

/* PRAMC1_PRCR1 */ CLR(PRAMC_PRCR1_P0_BO_DIS_MASK)|SET(PRAMC_PRCR1_FT_DIS_MASK), \

/* PRAMC2_PRCR1 */ CLR(PRAMC_PRCR1_P0_BO_DIS_MASK)|SET(PRAMC_PRCR1_FT_DIS_MASK), \

/* CONFIG_REG_GPR */ SET(CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC(5u))| \

/* ... */ SET(CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(3u)), \

/* FXOSC_CTRL */ CLR(FXOSC_CTRL_OSC_BYP_MASK)|SET(FXOSC_CTRL_COMP_EN_MASK)| \

/* ... */ SET(FXOSC_CTRL_EOCV(157u))|SET(FXOSC_CTRL_GM_SEL(12u))| \

/* ... */ SET(FXOSC_CTRL_OSCON_MASK), \

/* STDBY_ENABLE */ SET(FIRC_STDBY_ENABLE_STDBY_EN_MASK), \

/* MISCELLANEOUS_IN */ SET(SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE_MASK), \

/* PLLDV */ SET(PLL_PLLDV_ODIV2(2u))|SET(PLL_PLLDV_RDIV(CLOCK_PLL_PLLDV_RDIV))| \

/* ... */ SET(PLL_PLLDV_MFI(CLOCK_PLL_PLLDV_MFI)), \

/* PLLFD */ CLR(PLL_PLLFD_SDMEN_MASK)|CLR(PLL_PLLFD_SDM2_MASK)| \

/* ... */ CLR(PLL_PLLFD_SDM3_MASK)|CLR(PLL_PLLFD_MFN_MASK), \

/* PLLFM */ SET(PLL_PLLFM_SSCGBYP_MASK)|CLR(PLL_PLLFM_SPREADCTL_MASK)| \

/* ... */ CLR(PLL_PLLFM_STEPSIZE_MASK)|CLR(PLL_PLLFM_STEPNO_MASK), \

/* PLLODIV0 */ SET(PLL_PLLODIV_DIV(2u)), \

/* PLLODIV1 */ SET(PLL_PLLODIV_DIV(1u)), \

/* MUX_0_DC_0 */ SET(MC_CGM_MUX_0_DC_0_DIV(0u))|SET(MC_CGM_MUX_0_DC_0_DE_MASK), \

/* MUX_0_DC_1 */ SET(MC_CGM_MUX_0_DC_1_DIV(1u))|SET(MC_CGM_MUX_0_DC_1_DE_MASK), \

/* MUX_0_DC_2 */ SET(MC_CGM_MUX_0_DC_2_DIV(3u))|SET(MC_CGM_MUX_0_DC_2_DE_MASK), \

/* MUX_0_DC_3 */ SET(MC_CGM_MUX_0_DC_3_DIV(1u))|SET(MC_CGM_MUX_0_DC_3_DE_MASK), \

/* MUX_0_DC_4 */ SET(MC_CGM_MUX_0_DC_4_DIV(3u))|SET(MC_CGM_MUX_0_DC_4_DE_MASK), \

/* MUX_0_DC_5 */ SET(MC_CGM_MUX_0_DC_5_DIV(3u))|SET(MC_CGM_MUX_0_DC_5_DE_MASK), \

/* MUX_0_DC_6 */ SET(MC_CGM_MUX_0_DC_6_DIV(0u))|SET(MC_CGM_MUX_0_DC_6_DE_MASK), \

/* MUX_0_CSC */ SET(MC_CGM_MUX_0_CSC_SELCTL(8u))|SET(MC_CGM_MUX_0_CSC_CLK_SW_MASK) \

}

Best,

Vusal

Re: Incorrect PWM frequency

Robin_Shen — Wed, 31 Jan 2024 01:22:48 GMT

Hi Vusal,

Please check the frequency of CORE_CLK by CLKOUT_RUN pin.

For the formula of PWM frequency, please refer to S32K344 hardware PWM frequency. What value did you assign to B1?

Best Regards,
Robin
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Re: Incorrect PWM frequency

vusal — Wed, 31 Jan 2024 16:56:56 GMT

Hi @Robin_Shen ,

Thank you for your message.

I am using S32K3-T-BOX. I checked PTD14 pin which is located on Wifi (UART) pin, and for some reason it reads zero Hz. I have MSCR[110] configured for OBE, DSE, and SSS (0x07). I have also configured MUX_6_CSC to CORE_CLK (1_0000b) and can confirm in the MUX_6_CSS that the MUX is working correctly. MUX_6_DC_0[DIV] I left at default.

Regarding your question about B1, in my PWM output, B is my duty cycle value and does not affect the frequency (period) when I change it.

Thank you,
Vusal

Re: Incorrect PWM frequency

Robin_Shen — Thu, 01 Feb 2024 05:19:27 GMT

If you use S32DS+S32K3 RTD, it may be more convenient to use S32 Configuration Tool.

Re: Incorrect PWM frequency

vusal — Thu, 01 Feb 2024 19:58:10 GMT

Hi @Robin_Shen ,

Thank you for your reply.

Unfortunately, I can't use RTD and have to stick to bare-metal. I am in the aviation industry, and we can't use third party API's.

It seems like I should be able to configure correct frequency using PLLDV:

Thanks,

Vusal

Re: Incorrect PWM frequency

Robin_Shen — Fri, 02 Feb 2024 02:27:19 GMT

Hi Vusal,

Please refer to the attached bare-metal project. But please note that my development board uses 16MHz Crystal, so the PLL configuration is different from yours. PLL output 160MHz. PTD14(CLKOUT_RUN) output 160MHz/(7+1)=20MHz. (The Pad Type of PTD14 is standard plus switching up to 25MHz). PTA1(eMIOS0_CH9) output 16kHz PWM.

Best Regards,
Robin

Re: Incorrect PWM frequency

vusal — Fri, 02 Feb 2024 13:41:19 GMT

Hi @Robin_Shen ,

Thank you very much for this. I'll take a look.

Best,
Vusal

Re: Incorrect PWM frequency

vusal — Tue, 06 Feb 2024 20:11:37 GMT

Hi @Robin_Shen ,

I ran a few configurations; however, it seems that PTD14 on T-Box maybe not feasible for CLOCKOUT-RUN? I could not get PWM or CLOCKOUT-RUN show up on this pin. Would it be because it is tied to a reset?

Thanks,
Vusal

Re: Incorrect PWM frequency

Robin_Shen — Wed, 07 Feb 2024 09:43:51 GMT

Did you connect ESP8266? If not, I don't think it was the problem.

Please check the values of the relevant registers mentioned before to confirm whether they are configured correctly. Also, is the PWM frequency accurate after referring to the project I gave? Have you measured the frequency of crystal and is it accurate?

Re: Incorrect PWM frequency

vusal — Thu, 08 Feb 2024 19:07:31 GMT

Hi @Robin_Shen ,

Thanks for your message.

I have not connected ESP8266. Only GPIO shows up on PTD14. On adjacent pins, I can generate PWM, but not on PTD14.

PWM frequency is a bit off. For example, when I switch to PLL(160mHz) it shows 16131kHz with 10001 period. On FIRC (48mHz), it shows 4.836kHz.

For some reason, I can't run your project directly on my environment. I used your project as a reference and set the registers. I have checked the register values, and all seems correct to me, but maybe I missed something while configuring the PWM settings? Is there a particular pin that can measure the crystal, or do I need to hold a probe to it?

Thanks!
Vusal

Re: Incorrect PWM frequency

vusal — Tue, 20 Feb 2024 22:42:16 GMT

Hi @Robin_Shen ,

At last, we were able to get a clean 16mHz clock frequency on PLL. We changed the values around a bit for ODIV2, RDIV, and MFI bits in the PLLDV register.

Thanks for your help again.

Vusal