<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックSome Questions about SRAM</title>
    <link>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796035#M31120</link>
    <description>&lt;P&gt;I want to know why SRAM is divided into SRAM_ L and SRAM_ H. What is the difference between these two? What are they applicable to respectively? furthermore I found SRAM_ H and SRAM_ The addresses between L are discontinuous, why do we do this?&lt;/P&gt;&lt;P&gt;Thank！&lt;/P&gt;</description>
    <pubDate>Fri, 26 Jan 2024 10:56:09 GMT</pubDate>
    <dc:creator>Embedded_novice</dc:creator>
    <dc:date>2024-01-26T10:56:09Z</dc:date>
    <item>
      <title>Some Questions about SRAM</title>
      <link>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796035#M31120</link>
      <description>&lt;P&gt;I want to know why SRAM is divided into SRAM_ L and SRAM_ H. What is the difference between these two? What are they applicable to respectively? furthermore I found SRAM_ H and SRAM_ The addresses between L are discontinuous, why do we do this?&lt;/P&gt;&lt;P&gt;Thank！&lt;/P&gt;</description>
      <pubDate>Fri, 26 Jan 2024 10:56:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796035#M31120</guid>
      <dc:creator>Embedded_novice</dc:creator>
      <dc:date>2024-01-26T10:56:09Z</dc:date>
    </item>
    <item>
      <title>Re: Some Questions about SRAM</title>
      <link>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796091#M31124</link>
      <description>&lt;P&gt;It offers certain advantage for performance optimization.&lt;/P&gt;
&lt;P&gt;SRAM_L offers single-cycle access for core code bus whilst SRAM_U offers single-cycle access for core system bus. Other accesses are backdoor and these take two clocks.&lt;/P&gt;
&lt;P&gt;However SRAM address space is continuous, because SRAM_L extends downwards and SRAM_U extends upwards as you can see on the picture below:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_0-1706276924845.png" style="width: 416px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260287i9CDB6A838F3E339F/image-dimensions/416x293?v=v2" width="416" height="293" role="button" title="davidtosenovjan_0-1706276924845.png" alt="davidtosenovjan_0-1706276924845.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;davidtosenovjan_0-1706276924845.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 26 Jan 2024 13:50:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796091#M31124</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2024-01-26T13:50:00Z</dc:date>
    </item>
    <item>
      <title>Re: Some Questions about SRAM</title>
      <link>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796579#M31147</link>
      <description>Thank you very much for your answer！</description>
      <pubDate>Mon, 29 Jan 2024 05:25:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Some-Questions-about-SRAM/m-p/1796579#M31147</guid>
      <dc:creator>Embedded_novice</dc:creator>
      <dc:date>2024-01-29T05:25:17Z</dc:date>
    </item>
  </channel>
</rss>

