topic S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin < 6V))? in S32K

S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin < 6V))?

Eason_L — Fri, 12 Jan 2024 00:56:10 GMT

Hi,

Accroding to S32K344 EVB circuit.

Eason_L_0-1705020927232.png

1. The votage of FS26_VDEBUG is 7.2 (12*15/25), How can it enter debug mode(VDBG(2.5V < debug pin < 6V))?

2. What's the purpose of BJT circuit? It makes debug pin voltage drop to 0V after ~80ms

Thanks,

Eason

Re: S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin

Senlent — Fri, 12 Jan 2024 08:49:23 GMT

Hi@Eason_L

1.you may forget still have 10K resistor in the picture

Senlent_0-1705045702344.png

2.After VBAT_SW is powered on, it will turn on Q1 and pull FS26_VDEBUG low to 0V

Re: S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin

Eason_L — Fri, 12 Jan 2024 09:21:23 GMT

Hi Senlent,

Thanks for the first question. About second question, Why does it need to turn on Q1 and pull FS26_VDEBUG low to 0V? It seems unnecessary.

Eason_L_0-1705051135170.png

Re: S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin

Senlent — Mon, 15 Jan 2024 02:43:52 GMT

Hi@Eason_L

For OTP mode(Flash MODE), it is necessary.

please take a look at the below two chapters:

Rev.3

Chapter 23 OTP and Debug mode

When the OTP configuration is complete, the fail-safe state machine will start in Debug mode when the voltage at the DEBUG pin is below VNORM_max (NXP recommends applying 0 V or GND).

and Figure 72. OTP mode flowchart until safety outputs release

Re: S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin

1260784871 — Tue, 25 Jun 2024 06:17:26 GMT

after resistance R478 , the voltage test is still 7.2v，why？