SPD demo BIST config question

Pusoy — Fri, 22 Dec 2023 08:58:44 GMT

Hi,

Pre-Information:
In the "safety->STCU2" section of S32K3XXRM, there is a register related to PLL monitoring located at STCU2->RUNSW. According to the description, when our clock configuration uses PLL, we need to enable these two fields.

Pusoy_1-1703235115735.png

In the demo provided by S32K3 Safety Peripheral Drivers version 1.0.3 Design : Product Download : Files (flexnetoperations.com), PLL is enabled.

Pusoy_0-1703235078210.png

Based on the above information, these two bits should be set to 1 in the STCU2->RUNSW register in the demo.
And in the main.c file of the provided demo, the place where this register is set is in BIST_RUN()->Bist_Specific_Run()->Bist_SelfTestTrigger()->SAFETYBASE_REG_WRITE32(BIST_STCU_RUNSW_REG, BIST_STCU_RUNSW_RUN_BIT);

Pusoy_2-1703235253849.png

However, in the case where PLL is enabled in the clock configuration, the library driver provided by SPD does not set these two bits to 1.

1. Is this a design flaw or do users need to manually modify certain code?

Re: SPD demo BIST config question

petervlna — Thu, 28 Dec 2023 08:37:02 GMT

Hello,

1. Is this a design flaw or do users need to manually modify certain code?

Well, this would be the question to designers of the SW. But for sure if you want run the PLL for BIST, you need to set those bits.

If you like the feedback from SW owners, please submit a ticket at NXP.com so it will reach them.

Best regards,

Peter

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SPD demo BIST config question

Re: SPD demo BIST config question