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    <title>S32KのトピックRe: STCU2 PLL question</title>
    <link>https://community.nxp.com/t5/S32K/STCU2-PLL-question/m-p/1772944#M29545</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Yes, you have to enable them if you use PLL for tests.&lt;/P&gt;
&lt;P&gt;I guess SAF already has this enabled in some run function, but in case you have your own driver you have to take care of these bits.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
    <pubDate>Tue, 12 Dec 2023 08:42:42 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2023-12-12T08:42:42Z</dc:date>
    <item>
      <title>STCU2 PLL question</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-PLL-question/m-p/1771959#M29488</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;In the "safety-&amp;gt;STCU2" section of S32K3XXRM, there is a configuration register for PLL located at STCU2-&amp;gt;RUNSW.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;When our clock configuration uses PLL, do we need to enable these two fields?&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Pusoy_0-1702273354554.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/253707i25E60EA5F9BA994E/image-size/large?v=v2&amp;amp;px=999" role="button" title="Pusoy_0-1702273354554.png" alt="Pusoy_0-1702273354554.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;</description>
      <pubDate>Mon, 11 Dec 2023 05:43:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-PLL-question/m-p/1771959#M29488</guid>
      <dc:creator>Pusoy</dc:creator>
      <dc:date>2023-12-11T05:43:05Z</dc:date>
    </item>
    <item>
      <title>Re: STCU2 PLL question</title>
      <link>https://community.nxp.com/t5/S32K/STCU2-PLL-question/m-p/1772944#M29545</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Yes, you have to enable them if you use PLL for tests.&lt;/P&gt;
&lt;P&gt;I guess SAF already has this enabled in some run function, but in case you have your own driver you have to take care of these bits.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Tue, 12 Dec 2023 08:42:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/STCU2-PLL-question/m-p/1772944#M29545</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2023-12-12T08:42:42Z</dc:date>
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