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    <title>topic SRAM ECC Initialization for S32K344 in S32K</title>
    <link>https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1763329#M28971</link>
    <description>&lt;P&gt;Hello NXP Team,&lt;/P&gt;&lt;P&gt;Is their any example code of avoiding SRAM ECC Initialization for S32k344 if reset type is not destructive reset?&lt;/P&gt;&lt;P&gt;Any example project or start code would be really helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 24 Nov 2023 11:04:53 GMT</pubDate>
    <dc:creator>aadyaa</dc:creator>
    <dc:date>2023-11-24T11:04:53Z</dc:date>
    <item>
      <title>SRAM ECC Initialization for S32K344</title>
      <link>https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1763329#M28971</link>
      <description>&lt;P&gt;Hello NXP Team,&lt;/P&gt;&lt;P&gt;Is their any example code of avoiding SRAM ECC Initialization for S32k344 if reset type is not destructive reset?&lt;/P&gt;&lt;P&gt;Any example project or start code would be really helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Nov 2023 11:04:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1763329#M28971</guid>
      <dc:creator>aadyaa</dc:creator>
      <dc:date>2023-11-24T11:04:53Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM ECC Initialization for S32K344</title>
      <link>https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1764143#M29041</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/215692"&gt;@aadyaa&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;We need to modify the default startup_cm7.s file, so that SRAM ECC intialization can be skipped in case of Functional reset.&lt;/P&gt;
&lt;P&gt;Something like this:&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;RamInit:
/* Check MC_RGM DES register, if it's non-zero, jump to RAMInit_Start. (RAM init is needed if Destructive reset occurred) */
/* To make it work, customer should clear the MC_RGM DES register in application code. */
ldr r4, =MC_RGM_BASE_ADDR   /* 0x4028C000 */ 
ldr r4, [r4, #0x0]
cmp r4, #0x0
bne RamInit_Start
/* Check MC_RGM FES register, if the F_EXR bit or ST_DONE bit is set, jump to RAMInit_Start. */
/* RAM init is needed if external reset occurred, or BIST Done functional reset occurred. */
/* To make it work, customer should clear the MC_RGM FES F_EXR register bit in application code. */
ldr r4, =MC_RGM_BASE_ADDR
ldr r4, [r4, #0x8]
ldr r5, =MC_RGM_FES_MASK_RAM_INIT
and r4, r4, r5
cmp r4, #0x0
bne RamInit_Start
b SRAM_LOOP_END
RamInit_Start:
/* Initialize SRAM ECC */
ldr r0, =__RAM_INIT
cmp r0, 0
/* Skip if __SRAM_INIT is not set */
beq SRAM_LOOP_END
ldr r1, =__INT_SRAM_START
ldr r2, =__INT_SRAM_END&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Mon, 27 Nov 2023 14:58:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1764143#M29041</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2023-11-27T14:58:20Z</dc:date>
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