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    <title>topic My ticket in S32K</title>
    <link>https://community.nxp.com/t5/S32K/My-ticket/m-p/808416#M2884</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Not able to trigger&amp;nbsp;GPT interrupt:&lt;/P&gt;&lt;P&gt;MCAL: S32K148&lt;/P&gt;&lt;P&gt;MCAL Ver:&amp;nbsp;T40D2M10I0R0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are facing issue with the GPT, as the Interrupts are not getting triggered on Timer overflow. Below are the brief updates of what has been tried.&lt;/P&gt;&lt;P&gt;1.&amp;nbsp;&amp;nbsp;&amp;nbsp;We configured FTM0 (Ch0), used SYS CLK (80MHz) as clock source, and FTM_0_CH_0_CH_1_ISR as ISR.&lt;/P&gt;&lt;P&gt;We could see the counter running, TOF being set. But the Interrupt is not getting triggered.&lt;/P&gt;&lt;P&gt;Looking into the NXP drivers in the Gpt_Ipw_EnableInterrupt(), the Interrupts are not enabled for FTM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&amp;nbsp;&amp;nbsp;We also tried with using LPIT0. With the configurations done, we could see the relevant bits set accordingly in debugger for registers MSR, MIER, TCTRL.&lt;/P&gt;&lt;P&gt;Since, the ISR for LPIT0 (Gpt_LPIT_0_TIMER_0_ISR) is not available in the NXP driver, tried to have our own ISR. But we could not see the Interrupt getting triggered.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Config files are attached&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 Aug 2018 05:47:30 GMT</pubDate>
    <dc:creator>anwar_hussain</dc:creator>
    <dc:date>2018-08-21T05:47:30Z</dc:date>
    <item>
      <title>My ticket</title>
      <link>https://community.nxp.com/t5/S32K/My-ticket/m-p/808416#M2884</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Not able to trigger&amp;nbsp;GPT interrupt:&lt;/P&gt;&lt;P&gt;MCAL: S32K148&lt;/P&gt;&lt;P&gt;MCAL Ver:&amp;nbsp;T40D2M10I0R0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are facing issue with the GPT, as the Interrupts are not getting triggered on Timer overflow. Below are the brief updates of what has been tried.&lt;/P&gt;&lt;P&gt;1.&amp;nbsp;&amp;nbsp;&amp;nbsp;We configured FTM0 (Ch0), used SYS CLK (80MHz) as clock source, and FTM_0_CH_0_CH_1_ISR as ISR.&lt;/P&gt;&lt;P&gt;We could see the counter running, TOF being set. But the Interrupt is not getting triggered.&lt;/P&gt;&lt;P&gt;Looking into the NXP drivers in the Gpt_Ipw_EnableInterrupt(), the Interrupts are not enabled for FTM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&amp;nbsp;&amp;nbsp;We also tried with using LPIT0. With the configurations done, we could see the relevant bits set accordingly in debugger for registers MSR, MIER, TCTRL.&lt;/P&gt;&lt;P&gt;Since, the ISR for LPIT0 (Gpt_LPIT_0_TIMER_0_ISR) is not available in the NXP driver, tried to have our own ISR. But we could not see the Interrupt getting triggered.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Config files are attached&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 05:47:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/My-ticket/m-p/808416#M2884</guid>
      <dc:creator>anwar_hussain</dc:creator>
      <dc:date>2018-08-21T05:47:30Z</dc:date>
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