LPSPI CS to CLK time issue using S32K344uC

MVR — Wed, 15 Nov 2023 21:01:43 GMT

Hello everyone,

I'm facing a issue with the time between CS and CLCK on LPSPI, I would like to define it to 10us, but I can see 5us.

I'm using S32K344uC (S32K3X4EVB-Q172 board), I tested with LPSPI2 and LPSPI4. The SW version is: S32K3_RTD_2_0_1_D2207_ASR_REL_4_4_REV_0000_20220707.

Also I defined the clock of LPSPI to 20MHz:

When I defined like this (SpiTimeCs2Clk=0.000001):

It works as half (500ns):

When I defined as 10us:

The result is again the half of defined:

Also the clock should be 1MHz, but it is 2MHz:

Do you guys know why I'm facing this error?

If I defined the clock as 40MHz, it works fine, but the maximum time between CS and CLOCK that I can reach is 6.4us (1/40MHz * 255). I would like to reach 10us to wake up a driver:

Thank you,

MVR

Re: LPSPI CS to CLK time issue using S32K344uC

Robin_Shen — Fri, 17 Nov 2023 08:42:01 GMT

Hi MVR,

Thank you for the report.
Sorry for the inconvenience we bring you!
Please check if this issue has been fixed in newer S32K3 RTD.

Best Regards,
Robin
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topic LPSPI CS to CLK time issue using S32K344uC in S32K

LPSPI CS to CLK time issue using S32K344uC

Re: LPSPI CS to CLK time issue using S32K344uC