topic Re: LPSPI - Tx/Rx bytes different at different Baud Rates in S32K

LPSPI - Tx/Rx bytes different at different Baud Rates

ManishKK — Wed, 01 Nov 2023 05:56:40 GMT

I am using S32K344 on MR-CANHUB eval board from NxP. On that I am using S32K as the master to communicate with SPI Aardvark adapter as a slave on LPSPI4.

I have observed the following:

at 8Mhz, I see 5 bytes go out and 5 bytes come in, whereas
at 4Mhz, 6 bytes go out and 6 bytes come in.

The application is using a SyncTransmit API to transmit 10 bytes. I dont understand why all the 10 bytes are not Tx'ed by the S32K as master.

Attaching the example for reference.

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

danielmartynek — Wed, 01 Nov 2023 09:12:52 GMT

Hi @ManishKK,

Can you scope the signal and check the parameters specified in the S32K3xx DS (Table 44. LPSPI).

It was specified using GPIO-STANDARD_PLUS pins (MSCR_DSE = 1) that have better slew rate (7.3 5.0V (4.5V - 5.5V) GPIO Output AC Specification).

Since there is an issue with the Master, can you try with SAMPLE = 0, so that the Master can sample SCK internally?

Thank you,

Best regadrs,

Daniel

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

ManishKK — Wed, 01 Nov 2023 18:42:33 GMT

Daniel, Hi.

My LPSPI config looks like this:

/* SPI controller SpiPhyUnit_0 configuration. */
const Lpspi_Ip_ConfigType Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_Instance_4 =
{
4U, /* Instance */
/* CR */
(uint32)0,
/* CFGR1 */
(uint32)(LPSPI_CFGR1_PINCFG(0U) | LPSPI_CFGR1_PCSPOL(0U) | LPSPI_CFGR1_MASTER(1U) | LPSPI_CFGR1_SAMPLE(0U)),
#if (LPSPI_IP_SLAVE_SUPPORT == STD_ON)
(boolean)FALSE,
#endif
#if (LPSPI_IP_DMA_USED == STD_ON)
(boolean)TRUE,
(uint8)0, /* txDmaChannel */
(uint8)0, /* rxDmaChannel */
#if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
(uint8)4U, /* u8NumOfDmaFastTransfer */
Lpspi_Ip_CmdDmaFast_SpiPhyUnit_0,
U, /* Number of TCD Scatter Gather for Tx */
U, /* Number of TCD Scatter Gather for Rx */
Lpspi_Ip_ListTxDmaFastSGId_SpiPhyUnit_0,
Lpspi_Ip_ListRxDmaFastSGId_SpiPhyUnit_0,
#endif
#endif
LPSPI_IP_POLLING, /* Transfer mode */
(uint8)0U /* State structure element from the array */
#if (LPSPI_IP_DMA_USED == STD_ON)
,(boolean)FALSE /* If channels in HWunit are the same framesize. */
,(uint8)0U
#endif
};

As you can see, LPSPI_CFGR1_SAMPLE(0U)? Is this the parameter you are referring to by SAMPLE = 0?If it some other parameter, can you give me a full name (consistent with the one specified in Table 44)?

Thanks!

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

danielmartynek — Thu, 02 Nov 2023 12:29:16 GMT

Yes, this is the parameter.

Can you share the waveforms canptured by an analog oscilloscope?

What status does the Lpspi_Ip_SyncTransmit() function return?

I see you call the function before the scheduler is started, so we can exclude any FreeRTOS issues.

Thank you,

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

ManishKK — Wed, 08 Nov 2023 23:52:00 GMT

With MR-CANHUB NxP S32K344 board, I captured the screenshot of CLK and CS at 8 Mhz with an IMU board as the slave.

The CLK is unable to stay high.

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

ManishKK — Wed, 08 Nov 2023 23:53:57 GMT

Similarly, see screenshots of CS, CLK at 8 Mhz v/s 1 Mhz.

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

ManishKK — Wed, 08 Nov 2023 23:56:50 GMT

Another one at 4Mhz.

Re: LPSPI - Tx/Rx bytes different at different Baud Rates

danielmartynek — Fri, 10 Nov 2023 09:25:00 GMT

Hi @ManishKK,

As I mentioned in my first reply, the LPSPI specification in the DS was taken using GPIO-STANDARD_PLUS pins (MSCR_DSE = 1).

Because these pins have much better slew rate at a given capacitive load. Please refer to the DS, Table 26. GPIO Output AC Specification.

You use GPIO-STANDARD pin that can't drive the bus at this baudrate and the load (based on the waveforms you provided).

Best regards,

Daniel