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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>S32KのトピックRe: S32K116</title>
    <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1741127#M27899</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;The answer to the last problem was an OLD j-link version.&amp;nbsp;&lt;/P&gt;&lt;P&gt;With J-link version 12 all is ok now&lt;/P&gt;&lt;P&gt;Br&amp;nbsp; zorz&lt;/P&gt;</description>
    <pubDate>Tue, 17 Oct 2023 08:39:53 GMT</pubDate>
    <dc:creator>zorz</dc:creator>
    <dc:date>2023-10-17T08:39:53Z</dc:date>
    <item>
      <title>S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1735938#M27692</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am having an issue with the S32k116. The problem is the RESET signal because it is NOT stable it is having oscillation on the pin ( see the picture ).&amp;nbsp;&lt;/P&gt;&lt;P&gt;The design is pretty simple it is just a copy-paste from the EVAL board + additional IO and serial interfaces. On reset pin is just C and pull up. After applying the power I can see just this on the RESET pin.&amp;nbsp;&lt;/P&gt;&lt;P&gt;For debugging, I have S32DS and IAR-JLINK ( SEGGER ). I use SWD interface. When I connect RST signal from this debugging interface i have RED LED flashing on the debugger.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Does anyone have any idea what this means?&amp;nbsp;&amp;nbsp;Any help is much appreciated.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Br zorz&lt;/P&gt;</description>
      <pubDate>Mon, 09 Oct 2023 17:16:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1735938#M27692</guid>
      <dc:creator>zorz</dc:creator>
      <dc:date>2023-10-09T17:16:55Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1735958#M27695</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;/P&gt;&lt;P&gt;From all of the reading done .. I believe the problem is that the FLASH is empty and this is ok how the uC behaves.&amp;nbsp;&lt;/P&gt;&lt;P&gt;The issue now I have that I can not connect to the uC with S32DS and J-LINK to program something into it.&amp;nbsp;&lt;/P&gt;&lt;P&gt;This is what I have when I try to connect.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;SEGGER J-Link GDB Server V6.42a Command Line Version&lt;/P&gt;&lt;P&gt;JLinkARM.dll V6.42a (DLL compiled Feb 1 2019 18:00:08)&lt;/P&gt;&lt;P&gt;Command line: -if swd -device S32K116 -endian little -speed auto -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0 -nogui&lt;BR /&gt;-----GDB Server start settings-----&lt;BR /&gt;GDBInit file: none&lt;BR /&gt;GDB Server Listening port: 2331&lt;BR /&gt;SWO raw output listening port: 2332&lt;BR /&gt;Terminal I/O port: 2333&lt;BR /&gt;Accept remote connection: localhost only&lt;BR /&gt;Generate logfile: off&lt;BR /&gt;Verify download: on&lt;BR /&gt;Init regs on start: on&lt;BR /&gt;Silent mode: off&lt;BR /&gt;Single run mode: on&lt;BR /&gt;Target connection timeout: 0 ms&lt;BR /&gt;------J-Link related settings------&lt;BR /&gt;J-Link Host interface: USB&lt;BR /&gt;J-Link script: none&lt;BR /&gt;J-Link settings file: none&lt;BR /&gt;------Target related settings------&lt;BR /&gt;Target device: S32K116&lt;BR /&gt;Target interface: SWD&lt;BR /&gt;Target interface speed: auto&lt;BR /&gt;Target endian: little&lt;/P&gt;&lt;P&gt;Connecting to J-Link...&lt;BR /&gt;J-Link is connected.&lt;BR /&gt;Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46&lt;BR /&gt;Hardware: V8.00&lt;BR /&gt;S/N: 158004146&lt;BR /&gt;OEM: IAR&lt;BR /&gt;Checking target voltage...&lt;BR /&gt;Target voltage: 3.36 V&lt;BR /&gt;Listening on TCP/IP port 2331&lt;BR /&gt;Connecting to target...Connected to target&lt;BR /&gt;Waiting for GDB connection...Connected to 127.0.0.1&lt;BR /&gt;Reading all registers&lt;BR /&gt;Read 4 bytes @ address 0x00000000 (Data = 0xFFFFFFFF)&lt;BR /&gt;Read 2 bytes @ address 0x00000000 (Data = 0xFFFF)&lt;BR /&gt;Received monitor command: speed 1000&lt;BR /&gt;Target interface speed set to 1000 kHz&lt;BR /&gt;Received monitor command: clrbp&lt;BR /&gt;Received monitor command: reset&lt;BR /&gt;Resetting target&lt;BR /&gt;Received monitor command: halt&lt;BR /&gt;Halting target CPU...&lt;BR /&gt;...Target halted (PC = 0xFFFFFFFE)&lt;BR /&gt;Received monitor command: regs&lt;BR /&gt;R0 = FFFFFFFF, R1 = FFFFFFFF, R2 = FFFFFFFF, R3 = FFFFFFFF&lt;BR /&gt;R4 = FFFFFFFF, R5 = FFFFFFFF, R6 = FFFFFFFF, R7 = FFFFFFFF&lt;BR /&gt;R8 = FFFFFFFF, R9 = FFFFFFFF, R10= FFFFFFFF, R11= FFFFFFFF&lt;BR /&gt;R12= FFFFFFFF, R13= FFFFFFFC, MSP= FFFFFFFC, PSP= FFFFFFFC&lt;BR /&gt;R14(LR) = FFFFFFFF, R15(PC) = FFFFFFFE&lt;BR /&gt;XPSR F1000000, APSR F0000000, EPSR 01000000, IPSR 00000000&lt;BR /&gt;CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00&lt;BR /&gt;Reading all registers&lt;BR /&gt;WARNING: Failed to read memory @ address 0xFFFFFFFE&lt;BR /&gt;Received monitor command: speed auto&lt;BR /&gt;Select auto target interface speed (2000 kHz)&lt;BR /&gt;Received monitor command: flash breakpoints 1&lt;BR /&gt;Flash breakpoints enabled&lt;BR /&gt;Received monitor command: semihosting enable&lt;BR /&gt;Semi-hosting enabled (Handle on BKPT)&lt;BR /&gt;Received monitor command: semihosting IOClient 1&lt;BR /&gt;Semihosting I/O set to TELNET Client&lt;BR /&gt;Received monitor command: SWO DisableTarget 0xFFFFFFFF&lt;BR /&gt;SWO disabled successfully.&lt;BR /&gt;Received monitor command: SWO EnableTarget 0 0 0x1 0&lt;BR /&gt;WARNING: T-bit of XPSR is 0 but should be 1. Changed to 1.&lt;BR /&gt;ERROR: Failed to measure CPU clock frequency: second loop count is less than first one! (0&amp;lt;=13418)&lt;/P&gt;&lt;P&gt;Failed to enable SWO. Could not measure target CPU frequency.&lt;BR /&gt;Read 4 bytes @ address 0xFFFFFFFE (Data = 0x00000000)&lt;BR /&gt;Read 2 bytes @ address 0xFFFFFFFE (Data = 0x0000)&lt;BR /&gt;Downloading 192 bytes @ address 0x00000000 - Verified OK&lt;BR /&gt;Downloading 16 bytes @ address 0x00000400 - Verified OK&lt;BR /&gt;Downloading 15952 bytes @ address 0x00000410 - Verified OK&lt;BR /&gt;Downloading 15856 bytes @ address 0x00004260 - Verified OK&lt;BR /&gt;Downloading 1036 bytes @ address 0x00008050 - Verified OK&lt;BR /&gt;Downloading 8 bytes @ address 0x0000845C - Verified OK&lt;BR /&gt;Downloading 1008 bytes @ address 0x00008464 - Verified OK&lt;BR /&gt;WARNING: CPU could not be halted&lt;BR /&gt;ERROR: Failed to download RAMCode.&lt;BR /&gt;Failed to prepare for programming.&lt;BR /&gt;Failed to download RAMCode!&lt;BR /&gt;Can not read register 16 (XPSR) while CPU is running&lt;BR /&gt;Can not read register 20 (CFBP) while CPU is running&lt;BR /&gt;Can not read register 0 (R0) while CPU is running&lt;BR /&gt;Can not read register 1 (R1) while CPU is running&lt;BR /&gt;Can not read register 2 (R2) while CPU is running&lt;BR /&gt;Can not read register 3 (R3) while CPU is running&lt;BR /&gt;Can not read register 4 (R4) while CPU is running&lt;BR /&gt;Can not read register 5 (R5) while CPU is running&lt;BR /&gt;Can not read register 6 (R6) while CPU is running&lt;BR /&gt;Can not read register 7 (R7) while CPU is running&lt;BR /&gt;Can not read register 8 (R8) while CPU is running&lt;BR /&gt;Can not read register 9 (R9) while CPU is running&lt;BR /&gt;Can not read register 10 (R10) while CPU is running&lt;BR /&gt;Can not read register 11 (R11) while CPU is running&lt;BR /&gt;Can not read register 12 (R12) while CPU is running&lt;BR /&gt;Can not read register 14 (R14) while CPU is running&lt;BR /&gt;Can not read register 15 (R15) while CPU is running&lt;BR /&gt;Can not read register 17 (MSP) while CPU is running&lt;BR /&gt;Can not read r&lt;BR /&gt;Writing register (PC = 0x 410)&lt;BR /&gt;Read 4 bytes @ address 0x00000410 (Data = 0x00000000)&lt;BR /&gt;Read 2 bytes @ address 0x00000410 (Data = 0x0000)&lt;BR /&gt;Read 2 bytes @ address 0x00007AF4 (Data = 0x0000)&lt;BR /&gt;Received monitor command: clrbp&lt;BR /&gt;Received monitor command: reset&lt;BR /&gt;Resetting target&lt;BR /&gt;Received monitor command: halt&lt;BR /&gt;Halting target CPU...&lt;BR /&gt;...Target halted (PC = 0xFFFFFFFE)&lt;BR /&gt;Read 2 bytes @ address 0x00007AF4 (Data = 0xFFFF)&lt;BR /&gt;Received monitor command: regs&lt;BR /&gt;R0 = FFFFFFFF, R1 = FFFFFFFF, R2 = FFFFFFFF, R3 = FFFFFFFF&lt;BR /&gt;R4 = FFFFFFFF, R5 = FFFFFFFF, R6 = FFFFFFFF, R7 = FFFFFFFF&lt;BR /&gt;R8 = FFFFFFFF, R9 = FFFFFFFF, R10= FFFFFFFF, R11= FFFFFFFF&lt;BR /&gt;R12= FFFFFFFF, R13= FFFFFFFC, MSP= FFFFFFFC, PSP= FFFFFFFC&lt;BR /&gt;R14(LR) = FFFFFFFF, R15(PC) = FFFFFFFE&lt;BR /&gt;XPSR F1000000, APSR F0000000, EPSR 01000000, IPSR 00000000&lt;BR /&gt;CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00&lt;BR /&gt;Reading all registers&lt;BR /&gt;WARNING: Failed to read memory @ address 0xFFFFFFFE&lt;BR /&gt;Setting breakpoint @ address 0x00007AF4, Size = 2, BPHandle = 0x0001&lt;BR /&gt;Starting target CPU...&lt;BR /&gt;ERROR: Can not read register 15 (R15) while CPU is running&lt;BR /&gt;Reading all registers&lt;BR /&gt;ERROR: Can not read register 0 (R0) while CPU is running&lt;BR /&gt;ERROR: Can not read register 1 (R1) while CPU is running&lt;BR /&gt;ERROR: Can not read register 2 (R2) while CPU is running&lt;BR /&gt;ERROR: Can not read register 3 (R3) while CPU is running&lt;BR /&gt;ERROR: Can not read register 4 (R4) while CPU is running&lt;BR /&gt;ERROR: Can not read register 5 (R5) while CPU is running&lt;BR /&gt;ERROR: Can not read register 6 (R6) while CPU is running&lt;BR /&gt;ERROR: Can not read register 7 (R7) while CPU is running&lt;BR /&gt;ERROR: Can not read register 8 (R8) while CPU is running&lt;BR /&gt;ERROR: Can not read register 9 (R9) while CPU is running&lt;BR /&gt;ERROR: Can not read register 10 (R10) while CPU is running&lt;BR /&gt;ERROR: Can not read register 11 (R11) while CPU is running&lt;BR /&gt;ERROR: Can not read register 12 (R12) while CPU is running&lt;BR /&gt;ERROR: Can not read register 13 (R13) while CPU is running&lt;BR /&gt;ERROR: Can not read register 14 (R14) while CPU is running&lt;BR /&gt;ERROR: Can not read register 15 (R15) while CPU is running&lt;BR /&gt;ERROR: Can not read register 16 (XPSR) while CPU is running&lt;BR /&gt;ERROR: Can not read register 17 (MSP) while CPU is running&lt;BR /&gt;ERROR: Can not read register 18 (PSP) while CPU is running&lt;BR /&gt;ERROR: Can not read register 24 (PRIMASK) while CPU is running&lt;BR /&gt;ERROR: Can not read register 25 (BASEPRI) while CPU is running&lt;BR /&gt;ERROR: Can not read register 26 (FAULTMASK) while CPU is running&lt;BR /&gt;ERROR: Can not read register 27 (CONTROL) while CPU is running&lt;BR /&gt;Read 4 bytes @ address 0xDEADBEEE (Data = 0x00000000)&lt;BR /&gt;Read 4 bytes @ address 0xDEADBEEF (Data = 0x00000000)&lt;BR /&gt;Removing breakpoint @ address 0x00007AF4, Size = 2&lt;BR /&gt;Read 4 bytes @ address 0xDEADBEEE (Data = 0x00000000)&lt;BR /&gt;Read 2 bytes @ address 0xDEADBEEE (Data = 0x0000)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Br zorz&lt;/P&gt;</description>
      <pubDate>Tue, 10 Oct 2023 09:46:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1735958#M27695</guid>
      <dc:creator>zorz</dc:creator>
      <dc:date>2023-10-10T09:46:25Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1736470#M27721</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;/P&gt;&lt;P&gt;Update .. maybe it helps someone&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. reset signal is OK to be like that if the uC is "empty"&lt;/P&gt;&lt;P&gt;2. after the update of the j-link driver to the latest one, the debugger now can "partially" connect to the uC&amp;nbsp;&lt;/P&gt;&lt;P&gt;The current issue is&amp;nbsp;&lt;/P&gt;&lt;P&gt;*********************&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Connecting to target via SWD&lt;BR /&gt;InitTarget() start&lt;BR /&gt;SWD selected. Executing JTAG -&amp;gt; SWD switching sequence.&lt;BR /&gt;InitTarget() end - Took 173ms&lt;BR /&gt;Found SW-DP with ID 0x0BC11477&lt;BR /&gt;DPv0 detected&lt;BR /&gt;CoreSight SoC-400 or earlier&lt;BR /&gt;Scanning AP map to find all available APs&lt;BR /&gt;AP[2]: Stopped AP scan as end of AP map has been reached&lt;BR /&gt;AP[0]: AHB-AP (IDR: 0x04770031)&lt;BR /&gt;AP[1]: JTAG-AP (IDR: 0x001C0020)&lt;BR /&gt;Iterating through AP map to find AHB-AP to use&lt;BR /&gt;AP[0]: Core found&lt;BR /&gt;AP[0]: AHB-AP ROM base: 0xF0002000&lt;BR /&gt;CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)&lt;BR /&gt;Found Cortex-M0 r0p1, Little endian.&lt;BR /&gt;Connect fallback: Reset via Reset pin &amp;amp; Connect.&lt;BR /&gt;InitTarget() start&lt;BR /&gt;SWD selected. Executing JTAG -&amp;gt; SWD switching sequence.&lt;BR /&gt;InitTarget() end - Took 175ms&lt;BR /&gt;Found SW-DP with ID 0x0BC11477&lt;BR /&gt;DPv0 detected&lt;BR /&gt;CoreSight SoC-400 or earlier&lt;BR /&gt;AP map detection skipped. Manually configured AP map found.&lt;BR /&gt;AP[0]: AHB-AP (IDR: Not set)&lt;BR /&gt;AP[0]: Core found&lt;BR /&gt;AP[0]: AHB-AP ROM base: 0xF0002000&lt;BR /&gt;CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)&lt;BR /&gt;Found Cortex-M0 r0p1, Little endian.&lt;/P&gt;&lt;P&gt;****** Error: Failed to initialize CPU module in firmware because probe is low on memory (heap).&lt;BR /&gt;*************************************************************&lt;/P&gt;&lt;P&gt;Is it possible that j-link V8.0 is NOT compatible with the S32K1xx ?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Br zorz&lt;/P&gt;</description>
      <pubDate>Tue, 10 Oct 2023 09:47:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1736470#M27721</guid>
      <dc:creator>zorz</dc:creator>
      <dc:date>2023-10-10T09:47:29Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1736929#M27735</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi&amp;nbsp;zorz,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Yes. &lt;EM&gt;If there is no code programmed (a blank part), then the processor will periodically reset due to core lockups.&lt;/EM&gt;(Excerpted from &lt;A href="https://www.nxp.com/docs/en/application-note/AN12130.pdf" target="_self"&gt;AN12130&lt;/A&gt;)&amp;nbsp;After programmed, it will not reset anymore.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt; Latest&amp;nbsp;&lt;A href="https://www.segger.com/downloads/jlink/" target="_blank" rel="noopener" shape="rect"&gt;J-Link Software&lt;/A&gt;&amp;nbsp;may fix some bugs.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please confirm:&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;All VDD pins are powered by 3.3V&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;All VSS pins are connected to Ground&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;Refer to &lt;EM&gt;4.2 JTAG and TRACE interface&lt;/EM&gt; of &lt;A href="https://www.nxp.com/webapp/Download?colCode=AN5426" target="_self"&gt;AN5426&lt;/A&gt;&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;TCLK/SWD_CLK&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;external Pull-Down 10k-47k&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;TDI&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;external Pull-Up 10k-47k&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;TDO&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;external Pull-Up 10k-47k&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;TMS/SWD_DIO&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;external Pull-Up 10k-47k&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;RESET&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;external Pull-Up 10k-47k&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;I'm not sure the OEM &lt;STRONG&gt;IAR-JLINK (SEGGER)&lt;/STRONG&gt; you mentioned is able to connect S32K1, have you tried updating its firmware?&lt;BR /&gt;If you have S32K116EVB on hand, please try to connect this OEM &lt;STRONG&gt;IAR-JLINK (SEGGER)&lt;/STRONG&gt;&amp;nbsp;to the SWD interface on S32K116EVB and have a test.(Is it possible to connect the S32K116 that is working normally on the S32K116EVB board?)&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;If not able to connect to the chip, please check the values of MDM-AP status and control registers by refer to:&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://community.nxp.com/t5/S32K/Unbricking-S32K146/m-p/937227" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K/Unbricking-S32K146/m-p/937227&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Wed, 11 Oct 2023 01:21:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1736929#M27735</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-10-11T01:21:12Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1737133#M27749</link>
      <description>&lt;P&gt;HI Robin&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can confirm that the HW is the way you described. We are using 10k pull-ups. The VDD is 3.4V and VSS is to GND.&lt;/P&gt;&lt;P&gt;After the update of the JLINK and using J-link commander I am able to go this far:&amp;nbsp;&lt;/P&gt;&lt;P&gt;*******************************************&lt;/P&gt;&lt;P&gt;SEGGER J-Link Commander V7.92h (Compiled Oct 4 2023 16:23:14)&lt;BR /&gt;DLL version V7.92h, compiled Oct 4 2023 16:21:28&lt;/P&gt;&lt;P&gt;Connecting to J-Link via USB...O.K.&lt;BR /&gt;Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46&lt;BR /&gt;Hardware version: V8.00&lt;BR /&gt;J-Link uptime (since boot): N/A (Not supported by this model)&lt;BR /&gt;S/N: 158004146&lt;BR /&gt;OEM: IAR&lt;BR /&gt;VTref=0.000V&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Type "connect" to establish a target connection, '?' for help&lt;BR /&gt;J-Link&amp;gt;ts&lt;BR /&gt;Target connection not established yet but required for command.&lt;BR /&gt;Please specify device / core. &amp;lt;Default&amp;gt;: S32K116&lt;BR /&gt;Type '?' for selection dialog&lt;BR /&gt;Device&amp;gt;&lt;BR /&gt;Please specify target interface:&lt;BR /&gt;J) JTAG (Default)&lt;BR /&gt;S) SWD&lt;BR /&gt;T) cJTAG&lt;BR /&gt;TIF&amp;gt;s&lt;BR /&gt;Specify target interface speed [kHz]. &amp;lt;Default&amp;gt;: 4000 kHz&lt;BR /&gt;Speed&amp;gt;&lt;BR /&gt;Device "S32K116" selected.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Connecting to target via SWD&lt;BR /&gt;InitTarget() start&lt;BR /&gt;SWD selected. Executing JTAG -&amp;gt; SWD switching sequence.&lt;BR /&gt;InitTarget() end - Took 173ms&lt;BR /&gt;Found SW-DP with ID 0x0BC11477&lt;BR /&gt;DPv0 detected&lt;BR /&gt;CoreSight SoC-400 or earlier&lt;BR /&gt;Scanning AP map to find all available APs&lt;BR /&gt;AP[2]: Stopped AP scan as end of AP map has been reached&lt;BR /&gt;AP[0]: AHB-AP (IDR: 0x04770031)&lt;BR /&gt;AP[1]: JTAG-AP (IDR: 0x001C0020)&lt;BR /&gt;Iterating through AP map to find AHB-AP to use&lt;BR /&gt;AP[0]: Core found&lt;BR /&gt;AP[0]: AHB-AP ROM base: 0xF0002000&lt;BR /&gt;CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)&lt;BR /&gt;Found Cortex-M0 r0p1, Little endian.&lt;BR /&gt;Connect fallback: Reset via Reset pin &amp;amp; Connect.&lt;BR /&gt;InitTarget() start&lt;BR /&gt;SWD selected. Executing JTAG -&amp;gt; SWD switching sequence.&lt;BR /&gt;InitTarget() end - Took 175ms&lt;BR /&gt;Found SW-DP with ID 0x0BC11477&lt;BR /&gt;DPv0 detected&lt;BR /&gt;CoreSight SoC-400 or earlier&lt;BR /&gt;AP map detection skipped. Manually configured AP map found.&lt;BR /&gt;AP[0]: AHB-AP (IDR: Not set)&lt;BR /&gt;AP[0]: Core found&lt;BR /&gt;AP[0]: AHB-AP ROM base: 0xF0002000&lt;BR /&gt;CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)&lt;BR /&gt;Found Cortex-M0 r0p1, Little endian.&lt;/P&gt;&lt;P&gt;****** Error: Failed to initialize CPU module in firmware because probe is low on memory (heap).&lt;BR /&gt;*************************************************************&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Do you have any idea what is causing&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Failed to initialize CPU module in firmware because probe is low on memory (heap).&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;Br zorz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 11 Oct 2023 06:30:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1737133#M27749</guid>
      <dc:creator>zorz</dc:creator>
      <dc:date>2023-10-11T06:30:01Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116</title>
      <link>https://community.nxp.com/t5/S32K/S32K116/m-p/1741127#M27899</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;The answer to the last problem was an OLD j-link version.&amp;nbsp;&lt;/P&gt;&lt;P&gt;With J-link version 12 all is ok now&lt;/P&gt;&lt;P&gt;Br&amp;nbsp; zorz&lt;/P&gt;</description>
      <pubDate>Tue, 17 Oct 2023 08:39:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116/m-p/1741127#M27899</guid>
      <dc:creator>zorz</dc:creator>
      <dc:date>2023-10-17T08:39:53Z</dc:date>
    </item>
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