topic Re: S32K146 WatchDog disabled in S32K

S32K146 WatchDog disabled

ShaoTianzhi — Sun, 08 Oct 2023 03:37:55 GMT

Hello:

When I tested my code, I encountered an issue. In Debug mode, intentionally entering an infinite loop triggered the WatchDog Reset only once. After that, the code ran normally. However, when I tested it without Debug mode, I noticed that the WatchDog did not keep resetting continuously. Why could this be?

Re: S32K146 WatchDog disabled

Senlent — Sun, 08 Oct 2023 06:17:31 GMT

Hi@ShaoTianzhi

please check the register CS->DBG is set or not.

If this bit is configured to 1, in debugging mode, after encountering the breakpoint set by the user and stopping, the WDOG watchdog counter will still count, so that it will overflow and trigger the MCU reset soon.

please refer the demo wdog_interrupt_s32k146 which provided by S32 DS.

don't enable debug mode then try again.

Re: S32K146 WatchDog disabled

ShaoTianzhi — Sun, 08 Oct 2023 06:32:24 GMT

I didn't enable Debug Mode.

Does it have any impact if I don't enable interrupt?

Re: S32K146 WatchDog disabled

Senlent — Sun, 08 Oct 2023 06:45:55 GMT

Hi@ShaoTianzhi

The difference is that if you enable interrupts, then when the watchdog times out, an interrupt will be generated first and then the MCU will be reset.

Re: S32K146 WatchDog disabled

ShaoTianzhi — Mon, 09 Oct 2023 05:34:16 GMT

I didn't enable Debug Mode. After one WatchDog Reset, the infinite loop still continues to execute, but the WatchDog no longer resets. Upon observing the registers, after the WatchDog Reset, the initialization code for the WatchDog executes, but the EN register does not change to 1. UPDATE and PRES are also not configured. The CNT stops counting, and TOVAL remains at its default value of 0x0000FFFF.

Re: S32K146 WatchDog disabled

Senlent — Mon, 09 Oct 2023 05:41:37 GMT

Hi@ShaoTianzhi

Please provide your project and I will try to reproduce your problem.

Re: S32K146 WatchDog disabled

ShaoTianzhi — Tue, 10 Oct 2023 01:21:16 GMT

I'm sorry, but due to certain reasons, I'm unable to provide my code. The phenomenon I observed is that after a WDOG reset, the UPDATE register becomes zero, preventing the configuration of WDOG. Is there a way to resolve this? Could it be related to the BootLoader program?

Re: S32K146 WatchDog disabled

Senlent — Tue, 10 Oct 2023 02:14:51 GMT

Hi@ShaoTianzhi

It's hard to say because without your project I can't pinpoint the cause, I can only guess.

You can check whether Update is set at startup

Re: S32K146 WatchDog disabled

ShaoTianzhi — Wed, 11 Oct 2023 09:28:34 GMT

Thank you for your response. I found out that the BootLoader code set UPDATE to 0. The issue has been resolved.