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    <title>S32KのトピックRe: S32K3 Hardware Watchdog</title>
    <link>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720594#M26955</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;As for software-wise or hardware-wise, are you referring as if you should be able to see the external reset signal being asserted?&lt;/P&gt;
&lt;P&gt;Under the S32K3 reset sequences there are 3 types:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Power-ON Reset (POR)&lt;/LI&gt;
&lt;LI&gt;Destructive Reset&lt;/LI&gt;
&lt;LI&gt;Functional Reset&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;From the 3 types, the SWT module will generate a Functional Reset which is described as [Page 1205, S32K3xx Reference Manual, Rev. 6, 04/2023]:&lt;/P&gt;
&lt;P&gt;"Leads all the communication peripherals and cores to reset. The communication protocols' sanity &lt;BR /&gt;is not guaranteed and they are assumed to be reinitialized after reset. The SRAM content, and &lt;BR /&gt;the functionality of certain modules, is preserved across functional reset."&lt;/P&gt;
&lt;P&gt;As for the RESET_b pin, the following is described [Page 1222, S32K3xx Reference Manual, Rev. 6, 04/2023]:&lt;/P&gt;
&lt;P&gt;"The RESET_b pin offers the following uses if you configure it for the reset functionality:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Acts as an external destructive reset source&lt;/LI&gt;
&lt;LI&gt;&amp;nbsp;Acts as an indicator for the chip reset sequence for both functional and destructive reset sequences "&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;We may again be misunderstanding your request, if so we apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
    <pubDate>Mon, 11 Sep 2023 20:38:25 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2023-09-11T20:38:25Z</dc:date>
    <item>
      <title>S32K3 Hardware Watchdog</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720445#M26951</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Does the S32K3 series microcontrollers have hardware timers or software timers? Or is the term SWT only used as a naming convention and referred to as software in name only?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 11 Sep 2023 14:00:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720445#M26951</guid>
      <dc:creator>rexoplans</dc:creator>
      <dc:date>2023-09-11T14:00:06Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 Hardware Watchdog</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720536#M26953</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Looking at the title and from your question, we assume you are asking the following:&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;Does the S32K3 series microcontrollers have &lt;EM&gt;watchdog&amp;nbsp;&lt;/EM&gt;hardware timers or &lt;EM&gt;watchdog&amp;nbsp;&lt;/EM&gt;software timers?&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;If so, as you are implying, it is a naming convention. Since the SWT has registers that need configurations, it is a module embedded inside the MCU itself that requires an initialization [Page 2749, Chapter 67.5, S32K3xx Reference Manual, Rev. 6, 04/2023]. This can also be seen under the SWT Block Diagram [Page 2747, S32K3xx Reference Manual, Rev. 6, 04/2023]:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1694452584378.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/240461i218E56AEF5AF1E07/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1694452584378.png" alt="DanielAguirre_0-1694452584378.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Sep 2023 17:20:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720536#M26953</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-09-11T17:20:25Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 Hardware Watchdog</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720545#M26954</link>
      <description>"I actually couldn't explain the topic that confuses me exactly. Hardware-wise, I believe there is a Watchdog module, but when I tinkered with it a bit, it seemed to be just a timer. When the timeout value is reached, will the process of resetting the processor be done hardware-wise or software-wise?</description>
      <pubDate>Mon, 11 Sep 2023 17:48:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720545#M26954</guid>
      <dc:creator>rexoplans</dc:creator>
      <dc:date>2023-09-11T17:48:29Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 Hardware Watchdog</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720594#M26955</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;As for software-wise or hardware-wise, are you referring as if you should be able to see the external reset signal being asserted?&lt;/P&gt;
&lt;P&gt;Under the S32K3 reset sequences there are 3 types:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Power-ON Reset (POR)&lt;/LI&gt;
&lt;LI&gt;Destructive Reset&lt;/LI&gt;
&lt;LI&gt;Functional Reset&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;From the 3 types, the SWT module will generate a Functional Reset which is described as [Page 1205, S32K3xx Reference Manual, Rev. 6, 04/2023]:&lt;/P&gt;
&lt;P&gt;"Leads all the communication peripherals and cores to reset. The communication protocols' sanity &lt;BR /&gt;is not guaranteed and they are assumed to be reinitialized after reset. The SRAM content, and &lt;BR /&gt;the functionality of certain modules, is preserved across functional reset."&lt;/P&gt;
&lt;P&gt;As for the RESET_b pin, the following is described [Page 1222, S32K3xx Reference Manual, Rev. 6, 04/2023]:&lt;/P&gt;
&lt;P&gt;"The RESET_b pin offers the following uses if you configure it for the reset functionality:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Acts as an external destructive reset source&lt;/LI&gt;
&lt;LI&gt;&amp;nbsp;Acts as an indicator for the chip reset sequence for both functional and destructive reset sequences "&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;We may again be misunderstanding your request, if so we apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Sep 2023 20:38:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-Hardware-Watchdog/m-p/1720594#M26955</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-09-11T20:38:25Z</dc:date>
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