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    <title>topic S32K146:LPSPI Register TCR-&amp;gt;PRESCALE in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1717888#M26817</link>
    <description>&lt;P&gt;Hello:&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Recently, while studying the code, I found a problem,I set LPSPI2_CLK to 32MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShaoTianzhi_0-1693988238196.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239793iFE064BDE6065FA68/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ShaoTianzhi_0-1693988238196.png" alt="ShaoTianzhi_0-1693988238196.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But when I configure LPSPI2, the source clock is actually writable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShaoTianzhi_1-1693988443649.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239795i36D3B2429E909F8B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ShaoTianzhi_1-1693988443649.png" alt="ShaoTianzhi_1-1693988443649.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And, I haven't seen any operations to get the clock source frequency in both the LPSPI_DRV_MasterConfigureBus and LPSPI_SetBaudRate functions. Finally, when I set the Baud rate to 4MHz, the prescaler register responsible for dividing the clock (TCR-&amp;gt;PRESCALE) was set to 0x000h, which means no division, while my understanding is that its value should be 011b, corresponding to an 8x divider. Later, I tried to change the source clock to 4MHz, but TCR-&amp;gt;PRESCALE remained 0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I'd like to understand the relationship between the TCR-&amp;gt;PRESCALE register, "Baudrate", "source clock", and the "LPSPI2_CLK" configuration. How is the code arriving at a TCR-&amp;gt;PRESCALE value of 0, and what significance does setting 'LPSPI2_CLK' have? How does it differ from or relate to the "source clock"?&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 06 Sep 2023 08:32:54 GMT</pubDate>
    <dc:creator>ShaoTianzhi</dc:creator>
    <dc:date>2023-09-06T08:32:54Z</dc:date>
    <item>
      <title>S32K146:LPSPI Register TCR-&gt;PRESCALE</title>
      <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1717888#M26817</link>
      <description>&lt;P&gt;Hello:&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Recently, while studying the code, I found a problem,I set LPSPI2_CLK to 32MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShaoTianzhi_0-1693988238196.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239793iFE064BDE6065FA68/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ShaoTianzhi_0-1693988238196.png" alt="ShaoTianzhi_0-1693988238196.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But when I configure LPSPI2, the source clock is actually writable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShaoTianzhi_1-1693988443649.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239795i36D3B2429E909F8B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ShaoTianzhi_1-1693988443649.png" alt="ShaoTianzhi_1-1693988443649.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And, I haven't seen any operations to get the clock source frequency in both the LPSPI_DRV_MasterConfigureBus and LPSPI_SetBaudRate functions. Finally, when I set the Baud rate to 4MHz, the prescaler register responsible for dividing the clock (TCR-&amp;gt;PRESCALE) was set to 0x000h, which means no division, while my understanding is that its value should be 011b, corresponding to an 8x divider. Later, I tried to change the source clock to 4MHz, but TCR-&amp;gt;PRESCALE remained 0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I'd like to understand the relationship between the TCR-&amp;gt;PRESCALE register, "Baudrate", "source clock", and the "LPSPI2_CLK" configuration. How is the code arriving at a TCR-&amp;gt;PRESCALE value of 0, and what significance does setting 'LPSPI2_CLK' have? How does it differ from or relate to the "source clock"?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 06 Sep 2023 08:32:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1717888#M26817</guid>
      <dc:creator>ShaoTianzhi</dc:creator>
      <dc:date>2023-09-06T08:32:54Z</dc:date>
    </item>
    <item>
      <title>Re: S32K146:LPSPI Register TCR-&gt;PRESCALE</title>
      <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718367#M26846</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@ShaoTianzhi" target="_blank"&gt;Hi@ShaoTianzhi&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1694055967927.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239904iCF3B3CD0AAD75C56/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Senlent_0-1694055967927.png" alt="Senlent_0-1694055967927.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;1. The Baudrate here is actually the expected Baudrate&lt;BR /&gt;LPSPI_SetBaudRate()&lt;BR /&gt;This function will calculate an optimal frequency division value according to the expected baud rate you input and the module clock: &lt;U&gt;&lt;STRONG&gt;tcrPrescaleValue&lt;/STRONG&gt;&lt;/U&gt;&lt;/P&gt;
&lt;P&gt;The following function is the function to set the TCR register:&lt;BR /&gt;&lt;U&gt;LPSPI_SetTxCommandReg();&lt;/U&gt;&lt;/P&gt;
&lt;P&gt;2.Source clock&lt;/P&gt;
&lt;P&gt;It should be consistent with the clock configuration value in the frist picture you provided.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Sep 2023 03:16:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718367#M26846</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-09-07T03:16:19Z</dc:date>
    </item>
    <item>
      <title>Re: S32K146:LPSPI Register TCR-&gt;PRESCALE</title>
      <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718417#M26849</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Why, when I set the source clock to 32MHz and the Baud rate to 4MHz, do I see that the calculated value for tcrPrescaleValue is 0 instead of 3 when I check in Debug mode?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShaoTianzhi_0-1694064391388.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239921i2131FF5D65A5E113/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ShaoTianzhi_0-1694064391388.png" alt="ShaoTianzhi_0-1694064391388.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 07 Sep 2023 05:29:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718417#M26849</guid>
      <dc:creator>ShaoTianzhi</dc:creator>
      <dc:date>2023-09-07T05:29:51Z</dc:date>
    </item>
    <item>
      <title>Re: S32K146:LPSPI Register TCR-&gt;PRESCALE</title>
      <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718495#M26854</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@ShaoTianzhi" target="_blank"&gt;Hi@ShaoTianzhi&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;for SPI master mode:&lt;/P&gt;
&lt;P&gt;baudrate should equal to : functional clock / (TCR-&amp;gt;PRESCALE) / (CCR-&amp;gt;SCKDIV + 2)&lt;/P&gt;
&lt;P&gt;for example: clock source is 32Mhz, 4M baudrare&lt;/P&gt;
&lt;P&gt;test result:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1694069862609.png" style="width: 530px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239940i42C4B985A23584E1/image-dimensions/530x171?v=v2" width="530" height="171" role="button" title="Senlent_0-1694069862609.png" alt="Senlent_0-1694069862609.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_2-1694070018996.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239944i2BD55F6AA5520D28/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Senlent_2-1694070018996.png" alt="Senlent_2-1694070018996.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;TCR-&amp;gt;PRESCALE = 0 -&amp;gt; Divide by 1&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_3-1694070255244.png" style="width: 459px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239947i0F1D31B22B237443/image-dimensions/459x93?v=v2" width="459" height="93" role="button" title="Senlent_3-1694070255244.png" alt="Senlent_3-1694070255244.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;CCR-&amp;gt;PRESCALE = 0x06&lt;/P&gt;
&lt;P&gt;baudrate = 32 / 1 / (0x06 + 2) = 4Mhz.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 07 Sep 2023 07:04:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718495#M26854</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-09-07T07:04:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32K146:LPSPI Register TCR-&gt;PRESCALE</title>
      <link>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718539#M26857</link>
      <description>&lt;P&gt;Thank you for your answer.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Sep 2023 07:44:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K146-LPSPI-Register-TCR-gt-PRESCALE/m-p/1718539#M26857</guid>
      <dc:creator>ShaoTianzhi</dc:creator>
      <dc:date>2023-09-07T07:44:04Z</dc:date>
    </item>
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