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    <title>topic Re: S32K344 GPIO Reset Status Questions in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K344-GPIO-Reset-Status-Questions/m-p/1714908#M26661</link>
    <description>&lt;P&gt;Hi&lt;/P&gt;
&lt;P&gt;A1: PTA2 and PTA3 are allocated to FCCU fault output and PTA5 is for RESET_b. These pins can be configured via DCF records.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="S32K344 PTA2 PTA3 PTA5.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239035iC57E383072B1F54E/image-size/large?v=v2&amp;amp;px=999" role="button" title="S32K344 PTA2 PTA3 PTA5.png" alt="S32K344 PTA2 PTA3 PTA5.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;For FCCU: These pins will behave based on fault protocol used. Refer to chapter 53.3.5 EOUT interface of S32K3XXRM Rev.7.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239036iE20CBDA47ADE31C1/image-size/large?v=v2&amp;amp;px=999" role="button" title="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" alt="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;A3: See the MSCR reset value of the AC column, which contains these functions.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MSCR Reset value S32K344_IO Signal Table.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239037iD02FCEEC5754F032/image-size/large?v=v2&amp;amp;px=999" role="button" title="MSCR Reset value S32K344_IO Signal Table.png" alt="MSCR Reset value S32K344_IO Signal Table.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;/P&gt;</description>
    <pubDate>Thu, 31 Aug 2023 09:27:12 GMT</pubDate>
    <dc:creator>Robin_Shen</dc:creator>
    <dc:date>2023-08-31T09:27:12Z</dc:date>
    <item>
      <title>S32K344 GPIO Reset Status Questions</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-GPIO-Reset-Status-Questions/m-p/1713417#M26581</link>
      <description>&lt;P&gt;&lt;SPAN&gt;I'm using an S32K344, 257-pin BGA package.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to understand a little more about the reset status over the pins that we can see in the SK344_IOMUX.xlsx.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;1) What does DCF mean?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MVR_0-1692982014501.png" style="width: 491px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/238115i0EE35BA63A8750BE/image-dimensions/491x298?v=v2" width="491" height="298" role="button" title="MVR_0-1692982014501.png" alt="MVR_0-1692982014501.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2) And, if I would like to get the pin state on boot, before reach the "void main(void)" point, would I have to get the "Pad State After Selftest" column, correct?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;3) Is there a default state for direction (input/output), Driver type (push-pull/pullup...), alternate function and drive strength?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;4) What is the difference between DCF and MDM?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;P&gt;MVR&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 18:05:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-GPIO-Reset-Status-Questions/m-p/1713417#M26581</guid>
      <dc:creator>MVR</dc:creator>
      <dc:date>2023-08-29T18:05:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 GPIO Reset Status Questions</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-GPIO-Reset-Status-Questions/m-p/1714908#M26661</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;
&lt;P&gt;A1: PTA2 and PTA3 are allocated to FCCU fault output and PTA5 is for RESET_b. These pins can be configured via DCF records.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="S32K344 PTA2 PTA3 PTA5.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239035iC57E383072B1F54E/image-size/large?v=v2&amp;amp;px=999" role="button" title="S32K344 PTA2 PTA3 PTA5.png" alt="S32K344 PTA2 PTA3 PTA5.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;For FCCU: These pins will behave based on fault protocol used. Refer to chapter 53.3.5 EOUT interface of S32K3XXRM Rev.7.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239036iE20CBDA47ADE31C1/image-size/large?v=v2&amp;amp;px=999" role="button" title="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" alt="S32K3xx_DCF_clients Utest DCF Client Register Bits.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;A3: See the MSCR reset value of the AC column, which contains these functions.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MSCR Reset value S32K344_IO Signal Table.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/239037iD02FCEEC5754F032/image-size/large?v=v2&amp;amp;px=999" role="button" title="MSCR Reset value S32K344_IO Signal Table.png" alt="MSCR Reset value S32K344_IO Signal Table.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;/P&gt;</description>
      <pubDate>Thu, 31 Aug 2023 09:27:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-GPIO-Reset-Status-Questions/m-p/1714908#M26661</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-08-31T09:27:12Z</dc:date>
    </item>
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