s32k sai mclk problem

nullnullnull — Thu, 31 Aug 2023 00:57:25 GMT

a case ：

sample rate 96k tdm 8channel 32bit per word

bclk will be 24.576mhz

then, mclk should be 49.512mhz

why the frequency of mclk cannot be more than 24.576mhz in datasheet?

Re: s32k sai mclk problem

Robin_Shen — Fri, 01 Sep 2023 07:55:11 GMT

There is BYP Bit Clock Bypass in 75.6.1.6 Transmit Configuration 2 (TCR2) :

If set, it allows to bypass the bit clock divider, thus BCLK is divided by 1 of audio master clock.

Best Regards,
Robin
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s32k sai mclk problem

Re: s32k sai mclk problem