S32K中的主题 Re: [Security] about Memory Management

[Security] about Memory Management

Gideon — Tue, 15 Aug 2023 05:38:47 GMT

Architecture: FreeRTOS 10.2.1 with S32K144

Our security has the following requirement:
"Do not grant unnecessary processes or tasks the permission to read or write to memory regions through process boundaries or MMU."

Q1: Does the S32K144 support process boundaries or MMU mechanisms?
Q2: If yes, what is the setting to enable process boundaries or MMU?

Re: [Security] about Memory Management

danielmartynek — Tue, 15 Aug 2023 10:39:32 GMT

Hello @Gideon,

Unfortunately, the S32K1xx series do not have MMU.

MSCM_CPxCFG3 = 0x101.

MSCM_CPxCFG3[MMU] = 0.

The S32K1xx HW supports:

The system MPU prevents access of different bus masters to address ranges. It is typically intended for use by the safety application to prevent non-safety related modules access to the application's safety-relevant resources.
The peripheral bridge can restrict read and write access to individual I/O modules based on the origin of the access and its state (user mode/supervisor mode).
Register protection prevents individual registers from any manipulation until the registers are unlocked.

Regards,

Daniel

Re: [Security] about Memory Management

Gideon — Tue, 22 Aug 2023 10:52:28 GMT

the S32K1xx series do not have MMU ==> OK, I understand.
But does the S32K144 series with FreeRTOS 10.2.1 support Process boundary mechanisms？

Re: [Security] about Memory Management

danielmartynek — Wed, 30 Aug 2023 11:09:07 GMT

Hi @Gideon,

As I mentioned, the MCU has an MPU only.

FreeRTOS has MPU support for the ARM MPU.

However, the CM4 core on S32K144 does not have ARM MPU, there is NXP MPU on the bus instead.

You would need to implement it on your own. There is SDK MPU driver though.

Regards,

Daniel