S32KのトピックRe: S32K144 Power mode transitions

S32K144 Power mode transitions

Niuyanlin — Thu, 17 Aug 2023 01:34:30 GMT

NXP Team

Hello, I enabled the LPTMR timer to periodically wake up the MCU and wanted to switch directly from VLPS mode to RUN mode. However, during actual testing, I found that the MCU switched from VLPS mode to VLPR mode I have a few questions:

1. Process 4 shown in the following figure: How to understand switching from vlps to run

2. After the MCU is awakened, there is no need to initialize the clock (FIRC)

Niuyanlin_0-1692235437335.png

Niuyanlin_1-1692235536677.png

Re: S32K144 Power mode transitions

Senlent — Thu, 17 Aug 2023 08:18:31 GMT

Hi@Niuyanlin

Make sure that the clock source of LPTMR in low-power mode should be SIRC, and then disconnect the debugger before entering low-power mode

1. Process 4 shown in the following figure: How to understand switching from vlps to run

If it enters VLPS mode from run, then it is exit VLPS to RUN after waking up, not VPLS->VLPR->RUN

2. After the MCU is awakened, there is no need to initialize the clock (FIRC)

"STOP and VLPS mode exit sequence
Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR):
1. The on-chip regulator in the PMC, clock generators and internal power switches are restored. This step is valid only for VLPS and not for STOP as in STOP mode the PMC is in Run regulation.
2. System and bus clocks are enabled to all masters and slaves.(so the answer is yes)
3. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode."

Re: S32K144 Power mode transitions

Niuyanlin — Thu, 17 Aug 2023 09:15:06 GMT

@ Senlent
I output BUS through the CLKOUT pin_ CLK's clock was found to be 4M, not the 48M clock I set for RUN mode.Is it necessary to set it up somewhere

Re: S32K144 Power mode transitions

Senlent — Thu, 17 Aug 2023 09:27:19 GMT

Hi@Niuyanlin

I don't know how you set CLKOUT, what is the Divide Ratio?

Re: S32K144 Power mode transitions

Niuyanlin — Fri, 18 Aug 2023 01:20:44 GMT

@Senlent

The following figure shows my configuration:

Niuyanlin_3-1692321636985.png

Niuyanlin_1-1692319553594.png

Niuyanlin_2-1692321550134.png

Re: S32K144 Power mode transitions

Senlent — Fri, 18 Aug 2023 06:11:34 GMT

Hi@Niuyanlin

The clock needs to be set after VLPR wakes up, which is somewhat different from VLPS wakeup.

Senlent_0-1692338992973.png

Secondly, the clock output by clockout has an upper limit, which cannot exceed 20MHz.