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    <title>topic Re: LPSPI Manual Chip Select in S32K</title>
    <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692001#M25396</link>
    <description>&lt;P&gt;It is a possible but somewhat overcombined way. SPI transfer is initiated when CS is low but according CLK clock.&lt;/P&gt;
&lt;P&gt;If you drive CS line manually by general purpose output, content of TCR[PCS] is irrelevant.&lt;/P&gt;</description>
    <pubDate>Tue, 25 Jul 2023 07:35:36 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2023-07-25T07:35:36Z</dc:date>
    <item>
      <title>LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1690962#M25318</link>
      <description>&lt;P&gt;Hi, I am trying to configure my SPI2 port for operation using processor expert. But I see that there are already designated CS pins for operation. Could I configure the TCR register with PCS[0:3] and initiate transfer and manually control another GPIO pin as CS by pulling low? If so, what is the effect on the pin specified in the PCS field of the TCR register?&lt;/P&gt;</description>
      <pubDate>Mon, 24 Jul 2023 03:58:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1690962#M25318</guid>
      <dc:creator>Aravind_Vinas</dc:creator>
      <dc:date>2023-07-24T03:58:09Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692001#M25396</link>
      <description>&lt;P&gt;It is a possible but somewhat overcombined way. SPI transfer is initiated when CS is low but according CLK clock.&lt;/P&gt;
&lt;P&gt;If you drive CS line manually by general purpose output, content of TCR[PCS] is irrelevant.&lt;/P&gt;</description>
      <pubDate>Tue, 25 Jul 2023 07:35:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692001#M25396</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2023-07-25T07:35:36Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692082#M25404</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;But the TCR[PCS] points to some CS line always. Which means the line being pointed will get low whenever a transfer is initiated. Or is there a configuration on the SPI registers where it can ignore the TCR[PCS] setting?&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 25 Jul 2023 08:37:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692082#M25404</guid>
      <dc:creator>Aravind_Vinas</dc:creator>
      <dc:date>2023-07-25T08:37:41Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692856#M25446</link>
      <description>&lt;P&gt;Yes, but it is internal signal. If there is no routing done by PORT module (this internal signal to pin), it does not have any relevance.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jul 2023 08:14:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692856#M25446</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2023-07-26T08:14:28Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692884#M25447</link>
      <description>&lt;P&gt;If I understand this correctly, if the pin is not routed as ALT function to serve as PCS using the PORT engine, then this TCR[PCS] shall not have any effect on the pin.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jul 2023 08:35:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692884#M25447</guid>
      <dc:creator>Aravind_Vinas</dc:creator>
      <dc:date>2023-07-26T08:35:58Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692910#M25449</link>
      <description>&lt;P&gt;Yes, you are right.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jul 2023 08:55:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692910#M25449</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2023-07-26T08:55:58Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Manual Chip Select</title>
      <link>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692912#M25450</link>
      <description>&lt;P&gt;Kudos, thanks for the quick support!&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jul 2023 08:58:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPSPI-Manual-Chip-Select/m-p/1692912#M25450</guid>
      <dc:creator>Aravind_Vinas</dc:creator>
      <dc:date>2023-07-26T08:58:31Z</dc:date>
    </item>
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