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    <title>topic power cycle needed after flash erase/program in S32K</title>
    <link>https://community.nxp.com/t5/S32K/power-cycle-needed-after-flash-erase-program/m-p/1685164#M24951</link>
    <description>&lt;P&gt;I thought this problem was fixed, but it has come back.&lt;/P&gt;&lt;P&gt;We are using the s32k146 processor.&lt;/P&gt;&lt;P&gt;When I erase and write new data to the data flash memory, after the write, when reading from address 0x10000000, I get the old data and not the newly written data. Power cycling will fix this, but we don't want to have this limitation.&lt;/P&gt;&lt;P&gt;I asked this question before and got a response which led me to the OCM1 field of the OCMDR[1] register. I used this to disable and renable the cache, and tested and got good results. But I guess I was just lucky, because now I am back to having this problem.&lt;/P&gt;&lt;P&gt;Below is the code where we write to the flash memory, beginning and ending with the code to disable/enable the cache. Is something missing?&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;MSCM-&amp;gt;OCMDR[1] |= MSCM_OCMDR_OCM1(1); //disable data flash cache&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;EraseFlash(0); //erases the whole "block" however much that is, but more than just 8 bytes&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; FTFC_FCCOB0 = 0x7; //Program phrase&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; FTFC_FCCOB1 = 0x80;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB2 = 0;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB3 = 0;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data0 = ((int*) &amp;amp;incomingConfigs)[0];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data1 = ((int*) &amp;amp;incomingConfigs)[1];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC-&amp;gt;FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while ((FTFC-&amp;gt;FSTAT &amp;amp; FTFC_FSTAT_CCIF_MASK) == 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB3 = 8;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data0 = ((int*) &amp;amp;incomingConfigs)[2];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data1 = 0xFFFFFFFF;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC-&amp;gt;FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while ((FTFC-&amp;gt;FSTAT &amp;amp; FTFC_FSTAT_CCIF_MASK) == 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MSCM-&amp;gt;OCMDR[1] &amp;amp;= MSCM_OCMDR_OCM1(2); //enable data flash cache&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 10 Jul 2023 20:09:57 GMT</pubDate>
    <dc:creator>KelvinSmith</dc:creator>
    <dc:date>2023-07-10T20:09:57Z</dc:date>
    <item>
      <title>power cycle needed after flash erase/program</title>
      <link>https://community.nxp.com/t5/S32K/power-cycle-needed-after-flash-erase-program/m-p/1685164#M24951</link>
      <description>&lt;P&gt;I thought this problem was fixed, but it has come back.&lt;/P&gt;&lt;P&gt;We are using the s32k146 processor.&lt;/P&gt;&lt;P&gt;When I erase and write new data to the data flash memory, after the write, when reading from address 0x10000000, I get the old data and not the newly written data. Power cycling will fix this, but we don't want to have this limitation.&lt;/P&gt;&lt;P&gt;I asked this question before and got a response which led me to the OCM1 field of the OCMDR[1] register. I used this to disable and renable the cache, and tested and got good results. But I guess I was just lucky, because now I am back to having this problem.&lt;/P&gt;&lt;P&gt;Below is the code where we write to the flash memory, beginning and ending with the code to disable/enable the cache. Is something missing?&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;MSCM-&amp;gt;OCMDR[1] |= MSCM_OCMDR_OCM1(1); //disable data flash cache&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;EraseFlash(0); //erases the whole "block" however much that is, but more than just 8 bytes&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; FTFC_FCCOB0 = 0x7; //Program phrase&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; FTFC_FCCOB1 = 0x80;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB2 = 0;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB3 = 0;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data0 = ((int*) &amp;amp;incomingConfigs)[0];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data1 = ((int*) &amp;amp;incomingConfigs)[1];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC-&amp;gt;FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while ((FTFC-&amp;gt;FSTAT &amp;amp; FTFC_FSTAT_CCIF_MASK) == 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_FCCOB3 = 8;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data0 = ((int*) &amp;amp;incomingConfigs)[2];&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC_Data1 = 0xFFFFFFFF;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;FTFC-&amp;gt;FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while ((FTFC-&amp;gt;FSTAT &amp;amp; FTFC_FSTAT_CCIF_MASK) == 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MSCM-&amp;gt;OCMDR[1] &amp;amp;= MSCM_OCMDR_OCM1(2); //enable data flash cache&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 10 Jul 2023 20:09:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/power-cycle-needed-after-flash-erase-program/m-p/1685164#M24951</guid>
      <dc:creator>KelvinSmith</dc:creator>
      <dc:date>2023-07-10T20:09:57Z</dc:date>
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    <item>
      <title>Re: power cycle needed after flash erase/program</title>
      <link>https://community.nxp.com/t5/S32K/power-cycle-needed-after-flash-erase-program/m-p/1686695#M25068</link>
      <description>&lt;P&gt;On this device apparently there is no invalidate operation for flash pre-fetch buffer. &lt;BR /&gt;So you would apparently need to read from different address (out of the pre-fetched line) in order to load different line and then you should read new data you programmed before.&lt;/P&gt;</description>
      <pubDate>Wed, 12 Jul 2023 13:55:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/power-cycle-needed-after-flash-erase-program/m-p/1686695#M25068</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2023-07-12T13:55:55Z</dc:date>
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