topic Re: S32K142 SPI Read Operation Failed in S32K

S32K142 SPI Read Operation Failed

jingyinwong — Wed, 13 Jun 2018 10:01:17 GMT

Hi NXP Team,

I'm facing an issue related to SPI read operation on S32K142.

I tried to read the status register of a Winbond W25Q80DV serial flash memory. The datasheet mentions that I need to send an instruction of "0x05" in order to read the status register.

My SPI settings is as follows:

PCC->PCCn[PCC_LPSPI0_INDEX] = 0;
PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000;

LPSPI0->CR = 0x00000000;
LPSPI0->IER = 0x00000000;
LPSPI0->DER = 0x00000000;
LPSPI0->CFGR0 = 0x00000000;

LPSPI0->CFGR1 = 0x00000001;

LPSPI0->TCR = 0xD0000008;

LPSPI0->CCR = 0x04090808;

LPSPI0->FCR = 0x00000003;

LPSPI0->CR = 0x00000001;

PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[0]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI0_SCK */
PORTB->PCR[1]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI0_SIN */
PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI0_SOUT */
PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B17: MUX = ALT3, LPSPI0_PCS0 */

while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = 0x05; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve= LPSPI0->RDR; /* Read received data */
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */

I could not read the data (receive = 0).

CS0 went to a high state after 8 clock cycles (expecting CS0 to go to high state after 16 clock cycles).

Please advise on how to resolve the issue.

Thank you.

Best regards,

Jing Yin

Re: S32K142 SPI Read Operation Failed

danielmartynek — Wed, 13 Jun 2018 10:39:30 GMT

Hi,

I think you need to send at least 16 bits (0x5 + "xxxxxxxx") in a single frame, this will keep CS asserted between the bytes.

The Flash returns the content of the status register in the second byte.

Regards,

Daniel

Re: S32K142 SPI Read Operation Failed

中当陈 — Wed, 05 Sep 2018 06:46:04 GMT

兄弟，你好！

我也是参考官网LPSPI这个例程。遇到了和你类似的问题。你怎么解决这个问题的？

这是我的spi寄存器初始化代码：

PCC->PCCn[PCC_LPSPI2_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI2_INDEX] = 0xC2000000; /* Enable PCS=FIRDIV2 (30 MHz func'l clock) */

LPSPI2->CR = 0x00000000;
LPSPI2->IER = 0x00000000;
LPSPI2->DER = 0x00000000;
LPSPI2->CFGR0 = 0x00000000;
LPSPI2->CFGR1 = 0x00000001;
LPSPI2->TCR = 0x0000000f;
LPSPI2->CCR = 0x04090802;
LPSPI2->FCR = 0x00000003;
LPSPI2->CR = 0x00000001;

这是我发送函数：

void LPSPI2_transmit_16bits (uint32 send)
{
uint16 recieve = 0;
while((LPSPI2->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT == 0);
/* Wait for Tx FIFO available */
LPSPI2->TDR = send; /* Transmit data */
LPSPI2->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

然后用示波器发现MOSI没有输出。

Re: S32K142 SPI Read Operation Failed

中当陈 — Thu, 06 Sep 2018 01:44:38 GMT

已经解决，CFGR1的PINCFG由00->11即可。

Re: S32K142 SPI Read Operation Failed

jingyinwong — Thu, 06 Sep 2018 02:22:23 GMT

Hi 你好,

示波器显示的CLK waveform只有16个 clock cycles.

你可尝试把 TCR register 的 frame size (FRAMESZ) 改成 32-bit.

LPSPI2->TCR = 0x0000000f; --> LPSPI2->TCR = 0x0000001f;

(16-bit --> 32-bit)

Transmit 16 bits + Receive 16 bits = Total 32 bits.

希望能有所帮助.

Re: S32K142 SPI Read Operation Failed

中当陈 — Mon, 10 Sep 2018 14:19:30 GMT

多谢多谢，问题已经解决。