topic Re: Query about Reset problem in S32K344 in S32K

Query about Reset problem in S32K344

sun15021414801 — Sat, 03 Jun 2023 15:08:45 GMT

Hello,

I'm having a problem with s32k344 where the mcu keeps resetting while the code is running.

If the Lauterbach emulator is connected, there will be no problems, but if the chip is repowered, there will be problems.

I checked the value of the ME_RGM register and the Reset Reason and found it was HSE_SWT_RST reset.

I guess it has something to do with POR WDG,I want to close POR_WDG, Is there any sample code?

Thank you.

Re: Query about POR_WDG in S32K344

sun15021414801 — Sat, 03 Jun 2023 04:59:29 GMT

Sorry, my description is wrong. I check the MC_RGM register and see that the value of HSE_SWT_RST register is 1. Please help me judge the problem

Re: Query about Reset problem in S32K344

danielmartynek — Mon, 05 Jun 2023 10:01:16 GMT

Hello @sun15021414801,

Can you share the clock configuration?

Especially the CORE_CLK and the HSE_CLK freq.

Thank you,

BR, Daniel

Re: Query about Reset problem in S32K344

sun15021414801 — Tue, 20 Jun 2023 06:40:38 GMT

Thank you. There is a problem with the HSE CLK configuration.

Re: Query about Reset problem in S32K344

chosp — Fri, 16 Feb 2024 10:41:52 GMT

Next time the community would appreciate your progress being shared. I struggled with your very same problem, and I am indeed sharing the clocking issue solution details, with the S32K388, but I guess they apply to the entire S32K family.

Check AIPS_SLOW_CLK and HSE_CLK values. Also check DCM record regarding HSE_CLK_MODE_OPTION. With this, you know the ratio (either 1:2 or 1:4) that those clocks shall comply with.

If you are using S32K388 there is an extra step. The HSE_CLK_MODE_AND_GSKT_CTRL DCF record has to be verified, and modified accordingly to allow for the S32K388 selected clocking scheme between HSE and HSE_IAHB.

With this, the HSE_SWT_RST functional reset is gone!

@danielmartynek