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    <title>S32Kのトピックprotect Pheripheral with MPU</title>
    <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1668747#M23911</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Can MPU protect registers of Pheripherals?&amp;nbsp;&lt;/P&gt;&lt;P&gt;If the answer is yes, which MPU slave port does the pheriheral belong?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2023-06-13_17-38-20.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/227509i22B906D42BB53775/image-size/large?v=v2&amp;amp;px=999" role="button" title="Snipaste_2023-06-13_17-38-20.png" alt="Snipaste_2023-06-13_17-38-20.png" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 14 Jun 2023 01:44:06 GMT</pubDate>
    <dc:creator>Yellen</dc:creator>
    <dc:date>2023-06-14T01:44:06Z</dc:date>
    <item>
      <title>protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1668747#M23911</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Can MPU protect registers of Pheripherals?&amp;nbsp;&lt;/P&gt;&lt;P&gt;If the answer is yes, which MPU slave port does the pheriheral belong?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2023-06-13_17-38-20.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/227509i22B906D42BB53775/image-size/large?v=v2&amp;amp;px=999" role="button" title="Snipaste_2023-06-13_17-38-20.png" alt="Snipaste_2023-06-13_17-38-20.png" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 14 Jun 2023 01:44:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1668747#M23911</guid>
      <dc:creator>Yellen</dc:creator>
      <dc:date>2023-06-14T01:44:06Z</dc:date>
    </item>
    <item>
      <title>Re: protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1668975#M23927</link>
      <description>&lt;P&gt;Hi&amp;nbsp;Yellen,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please read Chapter 16 Peripheral Bridge (AIPS-Lite) of&lt;/SPAN&gt; &lt;A style="font-family: inherit; background-color: #ffffff;" href="https://www.nxp.com/webapp/Download?colCode=S32K1XXRM" target="_self" rel="nofollow noopener noreferrer"&gt;S32K1xx MCU Family - Reference Manual&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;And you can refer to:&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/S32K/How-to-use-s32k144-aips/m-p/1408446#M13870" target="_self"&gt;How to use s32k144 aips?&lt;/A&gt;&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/aips-demo-s32k118-zip/ta-p/1124234" target="_self"&gt;aips_demo_s32k118.zip&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Wed, 14 Jun 2023 06:51:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1668975#M23927</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-06-14T06:51:14Z</dc:date>
    </item>
    <item>
      <title>Re: protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1669016#M23935</link>
      <description>&lt;P&gt;Hi Robin,&lt;/P&gt;&lt;P&gt;Thanks for your response.&lt;/P&gt;&lt;P&gt;Refer to the Chapter 16, the MPU will not cover peripheral access protection. The pheriherals are protected by AIPS. Right?&lt;/P&gt;&lt;P&gt;But how to understand the MPU register can be protected by MPU as said below?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2023-06-13_17-38-20.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/227597iB7311FE9F895A71D/image-size/large?v=v2&amp;amp;px=999" role="button" title="Snipaste_2023-06-13_17-38-20.png" alt="Snipaste_2023-06-13_17-38-20.png" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 14 Jun 2023 07:25:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1669016#M23935</guid>
      <dc:creator>Yellen</dc:creator>
      <dc:date>2023-06-14T07:25:41Z</dc:date>
    </item>
    <item>
      <title>Re: protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1669857#M23981</link>
      <description>&lt;P&gt;&lt;STRONG&gt;14.1.2 Crossbar Switch slave assignments&lt;/STRONG&gt; The following table identifies the slaves connected to the Crossbar Switch and whether the system MPU protects them.&lt;BR /&gt;&lt;U&gt;System MPU does not protect access to peripheral registers, including system MPU's own registers.&lt;/U&gt; Protection is built into Peripheral Bridge (AIPS-Lite).&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="System MPU does not protect access to peripheral registers, including system MPU's own registers.jpg" style="width: 883px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/227789i524AFB09A22786A6/image-size/large?v=v2&amp;amp;px=999" role="button" title="System MPU does not protect access to peripheral registers, including system MPU's own registers.jpg" alt="System MPU does not protect access to peripheral registers, including system MPU's own registers.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I also can't understand: If the MPU registers are protected by the MPU&lt;/P&gt;</description>
      <pubDate>Thu, 15 Jun 2023 03:38:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1669857#M23981</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-06-15T03:38:46Z</dc:date>
    </item>
    <item>
      <title>Re: protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1670693#M24031</link>
      <description>&lt;P&gt;Suppose the MPU's register address is included in one region descriptor, will MPU report error if illegal access to MPU's register occured?&lt;/P&gt;</description>
      <pubDate>Fri, 16 Jun 2023 01:54:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1670693#M24031</guid>
      <dc:creator>Yellen</dc:creator>
      <dc:date>2023-06-16T01:54:50Z</dc:date>
    </item>
    <item>
      <title>Re: protect Pheripheral with MPU</title>
      <link>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1680829#M24704</link>
      <description>&lt;P&gt;I don't think so, but you can test it out.&lt;/P&gt;</description>
      <pubDate>Tue, 04 Jul 2023 02:39:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/protect-Pheripheral-with-MPU/m-p/1680829#M24704</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-07-04T02:39:51Z</dc:date>
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