topic Re: TRGMUX with SPI in S32K

S32K148 SPI+DMA ISSUE

zhouxiang1 — Tue, 06 Jun 2023 07:46:50 GMT

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When I use spi+dma as master to transmit 6 bytes, CS is controlled by GPIO, the TX interrupt happens at the end of the forth byte, but not at the end of the last byte. (set CS to HIGH in the TX interrupt) What can I do? Thanks!

Re: S32K148 SPI+DMA ISSUE

danielmartynek — Tue, 06 Jun 2023 09:13:35 GMT

Hello @zhouxiang1,

By the TX interrupt, I understand this is an interrupt at the end of the DMA transfer.

The DMA transfer completes as soon as the data are transfered to the LPSPI TX FIFO not at the end of the LPSPI transfer.

Why do you need a GPIO CS? The LPSPI module support continuous transfer mode that keeps the CS asserted between frames.

Regards,

Daniel

Re: Why do you need a GPIO CS?

zhouxiang1 — Tue, 06 Jun 2023 09:36:22 GMT

In some situation, CS need to sync with some other signals. For example, active CS first, and wait a postedge on some GPIO, then start SPI transmition. Could I implement this kind of requirement with hardware CS?

Re: Why do you need a GPIO CS?

danielmartynek — Tue, 06 Jun 2023 11:43:52 GMT

Do you mean Host Request?

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Thanks,

BR, Daniel

Re: TRGMUX with SPI

zhouxiang1 — Wed, 07 Jun 2023 00:47:13 GMT

Thanks for your suggestion about TRGMUX, I will read the chapter later. Are there some configurations what I can do to enable a interrupt at the end of LPSPI transfer?

Re: S32K148 SPI+DMA ISSUE

zhouxiang1 — Fri, 09 Jun 2023 04:43:52 GMT

I solve it. CS is controlled by GPIO, spi transfer is controlled by dma, deactive CS in the LPSPI interrupt (Transfer Complete Interrupt), but not in the dma interrupt.