S32KのトピックRe: S32K312 PLL_LOL Problem

S32K312 PLL_LOL Problem

zhengjianfei1 — Thu, 25 May 2023 06:39:43 GMT

Hi NXP,

We found S32K312 will reset while doing (ESD)Air discharge ±15kV test. And we found reset reason is PLL_LOL. Then we use NXP S32K312EVB-Q172 to do the same test, it will reset too.

We try to change GM_SET register to improve crystal diver strength,but it has no improvement. And we try to set DCMRWP3[9] to 1, S32K will not reset when PLL_LOL,but mcu will stop, only reset can recover it.

We need S32K3 keep running while the ESD test. Can cpu clock switch to FIRC while PLL_LOL? Could you give me some suggestions,Thanks!

Re: S32K312 PLL_LOL Problem

danielmartynek — Fri, 26 May 2023 12:43:51 GMT

Hi @zhengjianfei1,

Are you sure the FXOSC is that cause of the PLL Loss of Lock? Do you have the FXOSC clock monitor enabled?

It could be just the PLL. Is the lastmile regulator enabled?

You could try to change the system clock back to FIRC within the interrupt.

MUX_0_CSC[SAFE_SW] = 1

Regards,

Daniel

Re: S32K312 PLL_LOL Problem

zhengjianfei1 — Tue, 30 May 2023 03:08:29 GMT

Hi @danielmartynek ,

Thanks for your reply. CMU is disable and I am sure the reset reason is PLL Loss of Lock. When PLL LOL,MCU will reset. When set DCMRWP3[9] to 1, mcu will not reset while PLL LOL but mcu will stop running. Thus we cannot change the system clock back to FIRC when PLL LOL. We try to replace the Crystal Oscillator with a higher-power one, it seems better.

Re: S32K312 PLL_LOL Problem

danielmartynek — Tue, 16 Sep 2025 07:24:31 GMT

What do you mean by higher-power oscillator?

Did you disable the automatic level controller (FXOSC_CTRL[ALC_D] = 1)?

BR, Daniel

Re: S32K312 PLL_LOL Problem

zhengjianfei1 — Wed, 07 Jun 2023 10:58:09 GMT

Hi Daniel，

Thanks，disable automatic level controller can slove this problem.