<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: 9 Bit SPI with DMA in S32K</title>
    <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1658645#M23338</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188570"&gt;@maximillion&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Changes can be made to make the SDK functions support half-duplex.&lt;/P&gt;
&lt;P&gt;As mentioned in the reference manual, to configure LPSPI in a half-duplex it is required to define CFGR1[PINCFG] as 01b (SIN is used for both input and output data) or 10b (SOUT is used for both input and output data), CFGR1[OUTCFG] as 1b to configure to tristate when LPSPI_PCS is negated and depending of the implementation for 2-bit transfers CFGR1[PCSCFG] as any value or for 4-bit transfers as 1b.&lt;/P&gt;
&lt;P&gt;If we see from the SDK, LPSPI_SetPinConfigMode() needs to configure SDI as LPSPI_SDI_IN_OUT or SDO as LPSPI_SDO_IN_OUT and LPSPI_DATA_OUT_TRISTATE. These modifications would be for the register CFGR1 that I mentioned before.&lt;/P&gt;
&lt;P&gt;For more reference, the post I shared earlier talks about the situation with no SDK.&lt;/P&gt;</description>
    <pubDate>Fri, 26 May 2023 22:18:49 GMT</pubDate>
    <dc:creator>VaneB</dc:creator>
    <dc:date>2023-05-26T22:18:49Z</dc:date>
    <item>
      <title>9 Bit SPI with DMA</title>
      <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1655851#M23209</link>
      <description>&lt;P&gt;&lt;SPAN class=""&gt;I need to interface display with S32K142 MCU.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;My project hardware has only 3 wires (CSX, SDA and SCL) from the display side.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;I have to use 3-wire 9-bit mode only.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;So I changed SDK for 3 wire SPI configuration according to reference manual.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;So this is my MasterInit Function and I configured SDO pin as Input/Output.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="maximillion_0-1684853963295.png" style="width: 653px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/224507iC81CC560B5949AD0/image-dimensions/653x35?v=v2" width="653" height="35" role="button" title="maximillion_0-1684853963295.png" alt="maximillion_0-1684853963295.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;And processor expert configuration is depicted below.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="maximillion_1-1684854061826.png" style="width: 634px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/224509i66F81BB84A50D608/image-dimensions/634x62?v=v2" width="634" height="62" role="button" title="maximillion_1-1684854061826.png" alt="maximillion_1-1684854061826.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;and this is my function&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="maximillion_2-1684854105319.png" style="width: 483px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/224510iA442D5E08EFA652E/image-dimensions/483x226?v=v2" width="483" height="226" role="button" title="maximillion_2-1684854105319.png" alt="maximillion_2-1684854105319.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If so, I would like to know how to send 9 bits (1 D/C bit + 8 data bits) using SPI APIs. &lt;/SPAN&gt;&lt;SPAN&gt;MasterGetTransferStatus function returned STATUS_BUSY.&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;Is there any error?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;How should I do that process. Thanks for answering.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 15:04:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1655851#M23209</guid>
      <dc:creator>maximillion</dc:creator>
      <dc:date>2023-05-23T15:04:54Z</dc:date>
    </item>
    <item>
      <title>Re: 9 Bit SPI with DMA</title>
      <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1655976#M23215</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188570"&gt;@maximillion&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Take a look at&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32K/S32K-3-Wire-SPI-Drivers/td-p/1342666" target="_blank" rel="noopener"&gt;S32K 3-Wire SPI Drivers&lt;/A&gt;.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;B.R.&lt;/P&gt;
&lt;P&gt;VaneB&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 19:51:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1655976#M23215</guid>
      <dc:creator>VaneB</dc:creator>
      <dc:date>2023-05-23T19:51:54Z</dc:date>
    </item>
    <item>
      <title>Re: 9 Bit SPI with DMA</title>
      <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1656341#M23235</link>
      <description>The link you shared is not enough for me. I'm using S32SDK_S32K1xx_RTM_3.0.0 and when I look at the SDK what needs to be done for 3 wire communication is lpspi_pin_config_t and lpspi_data_out_config_t configuration. I made this configuration by modifying the SDK function. Does the S32SDK_S32K1xx_RTM_3.0.0 SDK version support this operation?</description>
      <pubDate>Wed, 24 May 2023 06:43:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1656341#M23235</guid>
      <dc:creator>maximillion</dc:creator>
      <dc:date>2023-05-24T06:43:56Z</dc:date>
    </item>
    <item>
      <title>Re: 9 Bit SPI with DMA</title>
      <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1658645#M23338</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188570"&gt;@maximillion&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Changes can be made to make the SDK functions support half-duplex.&lt;/P&gt;
&lt;P&gt;As mentioned in the reference manual, to configure LPSPI in a half-duplex it is required to define CFGR1[PINCFG] as 01b (SIN is used for both input and output data) or 10b (SOUT is used for both input and output data), CFGR1[OUTCFG] as 1b to configure to tristate when LPSPI_PCS is negated and depending of the implementation for 2-bit transfers CFGR1[PCSCFG] as any value or for 4-bit transfers as 1b.&lt;/P&gt;
&lt;P&gt;If we see from the SDK, LPSPI_SetPinConfigMode() needs to configure SDI as LPSPI_SDI_IN_OUT or SDO as LPSPI_SDO_IN_OUT and LPSPI_DATA_OUT_TRISTATE. These modifications would be for the register CFGR1 that I mentioned before.&lt;/P&gt;
&lt;P&gt;For more reference, the post I shared earlier talks about the situation with no SDK.&lt;/P&gt;</description>
      <pubDate>Fri, 26 May 2023 22:18:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1658645#M23338</guid>
      <dc:creator>VaneB</dc:creator>
      <dc:date>2023-05-26T22:18:49Z</dc:date>
    </item>
    <item>
      <title>Re: 9 Bit SPI with DMA</title>
      <link>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1658749#M23342</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/201913"&gt;@VaneB&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have to use SDK so according to your last post my 3-wire SPI configuration is true right?&lt;/P&gt;&lt;P&gt;First of all, I used DMA for SPI configuration via Processor Expert. So I have a question about this topic. I used LPSPI_DRV_MasterTransfer() functions and LPSPI_DRV_MasterGetTransferStatus() to send SPI data. There are 4 parameters in LPSPI_DRV_MasterTransfer().MasterTransfer function, one of them is receiveBuffer but I am using 3-wire SPI so I gave NULL parameter for receiver buffer. Is this valid? If yes how can I get data from slave device via txBuffer. Is this possible for the RTM3.0.0 SDK?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Secondly, does the LPSPI_DRV_MasterTransfer function need to be modified to send and receive data on the same DMA TX channel? Because I choose No DMA for Rx channel via processor expert.&lt;/P&gt;&lt;P&gt;I am not totally clear about this sentence "when LPSPI_PCS is negated" what does that mean "PCS negated". Isnt peripheral chip select value low right?&lt;/P&gt;</description>
      <pubDate>Sun, 28 May 2023 14:14:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/9-Bit-SPI-with-DMA/m-p/1658749#M23342</guid>
      <dc:creator>maximillion</dc:creator>
      <dc:date>2023-05-28T14:14:25Z</dc:date>
    </item>
  </channel>
</rss>

