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    <title>topic 回复： S32K3 LPCMP module Latency issues in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1655460#M23180</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If CCR1[SAMPLE_EN] is set to 1, at positive transition of the sample/window signal COUTA is sampled and filter counts specifies the number of consecutive samples that must agree before the comparator output filter accepts the sample as a new valid output state.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;BR, Petr&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 23 May 2023 07:59:45 GMT</pubDate>
    <dc:creator>PetrS</dc:creator>
    <dc:date>2023-05-23T07:59:45Z</dc:date>
    <item>
      <title>S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1640460#M22397</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have encountered some problem of S32K3 , LPCMP module.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="yinq_0-1682502183212.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/220913i6CB07129B1CD82C6/image-size/medium?v=v2&amp;amp;px=400" role="button" title="yinq_0-1682502183212.png" alt="yinq_0-1682502183212.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Which&amp;nbsp;position&amp;nbsp;may&amp;nbsp;Tper&amp;nbsp;appear&amp;nbsp;in&amp;nbsp;A,&amp;nbsp;B,&amp;nbsp;C,&amp;nbsp;D,&amp;nbsp;and&amp;nbsp;indicate&amp;nbsp;the&amp;nbsp;number&amp;nbsp;of&amp;nbsp;Tper&amp;nbsp;in&amp;nbsp;this&amp;nbsp;position?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 09:58:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1640460#M22397</guid>
      <dc:creator>yinq</dc:creator>
      <dc:date>2023-04-26T09:58:38Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1641578#M22457</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;there will be&amp;nbsp;2 Tper clock synchronization in the Window function (point B) and ((CCR1[FILT_CNT] x CCR1[FILT_PER]) + 1) x Tper clock for the Filter function (point D).&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Thu, 27 Apr 2023 12:26:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1641578#M22457</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-04-27T12:26:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1644500#M22590</link>
      <description>How to handle the cross clock domain transition from window function to filter when using mode # 7?</description>
      <pubDate>Thu, 04 May 2023 08:57:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1644500#M22590</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-04T08:57:48Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645089#M22616</link>
      <description>&lt;P&gt;&lt;SPAN&gt;How to handle the cross clock domain transition from window function to filter when using mode # 4A? Because in # 4A mode, the signal input to the filter is asynchronous with the filter clock window/sample.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 05 May 2023 01:06:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645089#M22616</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-05T01:06:47Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645090#M22617</link>
      <description>&lt;P&gt;&lt;SPAN&gt;How to handle the cross clock domain transition from window function to filter when using mode # 4A?&amp;nbsp;Because in # 4A mode, the signal input to the filter is asynchronous with the filter clock window/sample.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 05 May 2023 01:10:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645090#M22617</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-05T01:10:18Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645522#M22649</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;If CCR1[SAMPLE_EN] is set to 1, the low-pass filter samples COUTA on each positive transition of the sample/window input. Window signal must be of minimum 4 bus cycle pulse for window mode to function. The output state of the filter changes when all the consecutive CCR1[FILT_CNT] samples agree that the output value has changed.&lt;/P&gt;&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Fri, 05 May 2023 11:59:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645522#M22649</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-05-05T11:59:20Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645969#M22680</link>
      <description>&lt;P&gt;In 4A mode, such as filt_ cnt=5,couta is output by the bus clock.but,when couta go in filter, the clock of the filter at this time is asynchronous window/sample signal. The first sampling count of couta by window/sample may have metastable state,How to solve this problem？&lt;/P&gt;</description>
      <pubDate>Sun, 07 May 2023 03:48:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1645969#M22680</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-07T03:48:25Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1647927#M22785</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;in this mode, the path from the analog inputs to COUTA is combinational (unclocked). COUTA is then input to Filter and COUT is sampled signal. A first sample will always happen at uncertain time and can be from 0 to period of sampling signal. This cannot be influenced anyhow.&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Wed, 10 May 2023 11:51:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1647927#M22785</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-05-10T11:51:16Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1653714#M23077</link>
      <description>&lt;P class=""&gt;&lt;SPAN class=""&gt;When CCR1[SAMPLE_EN]=1, the window/sample signal acts as the clock of the filter, asynchronously with the bus clock? &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;If they are asynchronous, can window/sample signals count against COUTA directly?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 19 May 2023 09:05:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1653714#M23077</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-19T09:05:27Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1655460#M23180</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If CCR1[SAMPLE_EN] is set to 1, at positive transition of the sample/window signal COUTA is sampled and filter counts specifies the number of consecutive samples that must agree before the comparator output filter accepts the sample as a new valid output state.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;BR, Petr&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 07:59:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1655460#M23180</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-05-23T07:59:45Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1658054#M23317</link>
      <description>&lt;P&gt;So,is the working clock of the filter a bus clock? window_sample signal is not the working clock of the filter?&lt;/P&gt;</description>
      <pubDate>Fri, 26 May 2023 03:44:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1658054#M23317</guid>
      <dc:creator>zhanguiyang</dc:creator>
      <dc:date>2023-05-26T03:44:53Z</dc:date>
    </item>
    <item>
      <title>回复： S32K3 LPCMP module Latency issues</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1660411#M23416</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;this is a feedback I got from Apps team.&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN class=""&gt;When CCR1[SAMPLE_EN]=1, the window/sample signal acts as the clock of the filter, asynchronously with the bus clock?&amp;nbsp;&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;Yes&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;STRONG&gt;If they are asynchronous, can window/sample signals count against COUTA directly?&lt;/STRONG&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;I can understand your mean. But you can refer the attachments which include the detail of filter, sample and window.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN class=""&gt;So, is the working clock of the filter a bus clock? Window_sample signal is not the working clock of the filter?&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;The LPCMP working clock of the filter is bus clock. Window_sample signal is the sample input and is not the working clock of the filter.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Wed, 31 May 2023 10:16:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-LPCMP-module-Latency-issues/m-p/1660411#M23416</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-05-31T10:16:43Z</dc:date>
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