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    <title>S32KのトピックI2C baudrate issue</title>
    <link>https://community.nxp.com/t5/S32K/I2C-baudrate-issue/m-p/1646963#M22735</link>
    <description>&lt;P&gt;Hello Team,&lt;/P&gt;&lt;P&gt;I am trying to configure the I2C module in Master mode in S32 Design studio for S32K144 uC.&lt;/P&gt;&lt;P&gt;I want the speed to be 400kbps using the LPI2C0 module.&lt;/P&gt;&lt;P&gt;Upon generating the driver code &amp;amp; initializing, I see that the communication happens but at a slightly lower speed. The probe on the SCL line shows a clock of ~386kbps.The clock source for I2C is&amp;nbsp;CLK_SRC_SIRC_DIV2 &amp;amp; the CPU clock is 48MHz with a external crystal oscillator.&lt;/P&gt;&lt;P&gt;Need your support to identify where I would be going wrong.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 09 May 2023 08:35:33 GMT</pubDate>
    <dc:creator>Punit_01</dc:creator>
    <dc:date>2023-05-09T08:35:33Z</dc:date>
    <item>
      <title>I2C baudrate issue</title>
      <link>https://community.nxp.com/t5/S32K/I2C-baudrate-issue/m-p/1646963#M22735</link>
      <description>&lt;P&gt;Hello Team,&lt;/P&gt;&lt;P&gt;I am trying to configure the I2C module in Master mode in S32 Design studio for S32K144 uC.&lt;/P&gt;&lt;P&gt;I want the speed to be 400kbps using the LPI2C0 module.&lt;/P&gt;&lt;P&gt;Upon generating the driver code &amp;amp; initializing, I see that the communication happens but at a slightly lower speed. The probe on the SCL line shows a clock of ~386kbps.The clock source for I2C is&amp;nbsp;CLK_SRC_SIRC_DIV2 &amp;amp; the CPU clock is 48MHz with a external crystal oscillator.&lt;/P&gt;&lt;P&gt;Need your support to identify where I would be going wrong.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 09 May 2023 08:35:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/I2C-baudrate-issue/m-p/1646963#M22735</guid>
      <dc:creator>Punit_01</dc:creator>
      <dc:date>2023-05-09T08:35:33Z</dc:date>
    </item>
    <item>
      <title>Re: I2C baudrate issue</title>
      <link>https://community.nxp.com/t5/S32K/I2C-baudrate-issue/m-p/1647539#M22762</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@Punit_01" target="_blank"&gt;Hi@Punit_01&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;This can be explained.&lt;/P&gt;
&lt;P&gt;For details, you can refer to &lt;EM&gt;&lt;STRONG&gt;S32K-RM Chapter: 52.3.2.4 Timing Parameters&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;The SCL clock is not only determined by the module clock, but also affected by other parameters, including SCL_LATENCY,&lt;/P&gt;
&lt;P&gt;The latency parameters are defined in the following table, these parameters assume the&lt;BR /&gt;risetime is less than one LPI2C functional clock cycle. The risetime depends on a number&lt;BR /&gt;of factors, including the I/O propagation delay, &lt;STRONG&gt;the I2C bus loading and the external pullup&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;resistor sizing&lt;/STRONG&gt;. A larger risetime will increase the number of cycles that the signal&lt;BR /&gt;takes to propagate through the synchronizer (and glitch filter), which increases the&lt;BR /&gt;latency.&lt;/P&gt;
&lt;P&gt;In summary, the difference in the electrical characteristics of the external circuit will also affect the SCK.&lt;/P&gt;</description>
      <pubDate>Wed, 10 May 2023 03:19:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/I2C-baudrate-issue/m-p/1647539#M22762</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-05-10T03:19:44Z</dc:date>
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