topic Re: S32K148 LPSPI match configuration in S32K

S32K148 LPSPI match configuration

SONGTAOSI — Tue, 25 Apr 2023 08:06:52 GMT

Hi,

when I test the LPSPI_CFGR1_MATCFG bit ,There is one question that bothers me。

I configure LPSPI0 as master,LPSPI1 as slave. LPSPI1 transfer 5 datas[0x64,0x63,0x62,0x61,0x60] to LPSPI0, and

LPSPI0->CFGR1 |= LPSPI_CFGR1_MATCFG(3);

LPSPI0->IER |= LPSPI_IER_DMIE_MASK;//LPSPI_IER_DMIE_MASK;
LPSPI0->TCR |= LPSPI_TCR_CONT_MASK; //连续传输

LPSPI0->CFGR0 |= LPSPI_CFGR0_RDMO_MASK; //仅接收匹配

LPSPI0->DMR0 = 0x60; //最后一个数据进行匹配；
LPSPI0->DMR1 = 0x59;

After testing, I found that the last one data can't match with DMR0 and DMR1,regardless LPSPI_CFGR1_MATCFG(3) or 4,5,6,7.

Looking forward to your reply！Thanks.

Re: S32K148 LPSPI match configuration

danielmartynek — Tue, 25 Apr 2023 13:39:18 GMT

Hi @SONGTAOSI,

You use the continuous transfer mode (CONT = 1).

Do you terminate the continous transfer with a new TCR command?

Thank you,

BR, Daniel

Re: S32K148 LPSPI match configuration

SONGTAOSI — Wed, 26 Apr 2023 00:52:01 GMT

Thank you for your reply，but I'm sorry I didn't understand "Do you terminate the continous transfer with a new TCR command? " . I only config CONT=1，PCS is always keep asserted. I can match 4 datas except the last one.

Re: S32K148 LPSPI match configuration

danielmartynek — Wed, 26 Apr 2023 07:38:23 GMT

Hello @SONGTAOSI,

Can you negate the PCS (terminate the transfer) after the last frame?

This is done by writing the TCR FIFO with a new command.

danielmartynek_0-1682494644910.png

Thanks,

BR, Daniel

Re: S32K148 LPSPI match configuration

SONGTAOSI — Thu, 27 Apr 2023 12:26:04 GMT

Hi,

Your answer is very useful,Thank you so much.But I have another doubt.

if i transfer data quantity exceed 4, it should add a delay between Transfer and new TCR.

LPSPI_DRV_MasterTransfer(INST_LPSPI_1, master_buffer.tx, master_buffer.rx, 5);

delayCycles(100);

LPSPI_SetTxCommandReg(LPSPI0, &txCmdCfgSet );

the picture is add delay,it's ok

SONGTAOSI_0-1682598094814.png

this picture is not add delay, after transfer 4 data,the PCS is negate.

SONGTAOSI_1-1682598328518.png

Is this because the FIFO size Max is 4 word?

Re: S32K148 LPSPI match configuration

danielmartynek — Thu, 27 Apr 2023 12:42:32 GMT

Hi @SONGTAOSI,

The SDK driver should terminate the transfer in the CONT mode after the 5th byte, there is no need to do it in the user code.

Which version of the SDK do you use?

You use the non-blocking transfer function which returns immediately while the transfer is still ongoing. Thus the delay. But you can use the blocking function instead.

Do you need the CONT mode though?

You can simply set the frame size to 40bits and leave CONT = 0.

Regards,

Daniel