<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックS32k148</title>
    <link>https://community.nxp.com/t5/S32K/S32k148/m-p/1640507#M22402</link>
    <description>&lt;P&gt;Hello sir, can I ask for some support.&lt;/P&gt;&lt;P&gt;&amp;nbsp; I got some problem, when I use S32K148 on a item, it gose wrong&amp;nbsp; and the phenomenon is that when trigger the software reset, the reset pin continues to pull down &lt;SPAN&gt;sporadicly. It happened rarely but it confuses me really&lt;/SPAN&gt;&amp;nbsp;could you please me tell why would it happen.&lt;/P&gt;</description>
    <pubDate>Wed, 26 Apr 2023 10:54:59 GMT</pubDate>
    <dc:creator>SYP</dc:creator>
    <dc:date>2023-04-26T10:54:59Z</dc:date>
    <item>
      <title>S32k148</title>
      <link>https://community.nxp.com/t5/S32K/S32k148/m-p/1640507#M22402</link>
      <description>&lt;P&gt;Hello sir, can I ask for some support.&lt;/P&gt;&lt;P&gt;&amp;nbsp; I got some problem, when I use S32K148 on a item, it gose wrong&amp;nbsp; and the phenomenon is that when trigger the software reset, the reset pin continues to pull down &lt;SPAN&gt;sporadicly. It happened rarely but it confuses me really&lt;/SPAN&gt;&amp;nbsp;could you please me tell why would it happen.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 10:54:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32k148/m-p/1640507#M22402</guid>
      <dc:creator>SYP</dc:creator>
      <dc:date>2023-04-26T10:54:59Z</dc:date>
    </item>
    <item>
      <title>Re: S32k148</title>
      <link>https://community.nxp.com/t5/S32K/S32k148/m-p/1642056#M22480</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;For all reset sources, the RESET_B pin is driven low by the MCU for at least 128 bus clock cycles and until flash memory initialization has completed.&lt;/EM&gt; It is normal for &lt;STRONG&gt;Software reset (SW)&lt;/STRONG&gt; as one of these reset sources to drive the RESET_B pin low for at least 128 bus clock cycles.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="25.2.4 Reset pin.png" style="width: 872px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/221208iF4804AED211374AA/image-size/large?v=v2&amp;amp;px=999" role="button" title="25.2.4 Reset pin.png" alt="25.2.4 Reset pin.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Can you post a waveform obtained by an oscilloscope to show that &lt;STRONG&gt;the reset pin continues to pull down sporadically&lt;/STRONG&gt;?&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 07:09:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32k148/m-p/1642056#M22480</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2023-04-28T07:09:07Z</dc:date>
    </item>
  </channel>
</rss>

