lpSPI0 Configuration using polling method - S32K144-Q100

SivakumarMariappan — Tue, 04 Apr 2023 21:24:47 GMT

Here is the copy of the init code plz.

void LPSPI0_init_master(void) {
PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
LPSPI0->CR = 0x00000000; /* Disable module for configuration */
LPSPI0->IER = 0x00000000; /* Interrupts not used */
LPSPI0->DER = 0x00000000; /* DMA not used */
LPSPI0->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */
LPSPI0->CFGR1 = 0x00000001; /* Configurations: master mode*/
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */
LPSPI0->TCR = 0x5100001F; /* Transmit cmd: PCS1, 32bits, prescale func'l clk by 4. */
/* CPOL=0: SCK inactive state is low */
/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/
/* PRESCALE=2: Functional clock divided by 2**2 = 4 */
/* PCS=3: Transfer using PCS3 */
/* LSBF=0: Data is transferred MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=15: # bits in frame = 31+1=32 */
LPSPI0->CCR = 0x04090808; /* Clk dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
LPSPI0->FCR = 0x00000003; /* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */

LPSPI0->CR = 0x00000009; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */

I would like to transmit this code using polling method. Please help me out on the following.

1. What condition to check before transmit data (updating FIFO Tx buffer)

2. What is the condition to check when Data Transmission is completed

BTW Will this code work please?

void LPSPI0_transmit_32bits(uint32_t send) {
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT == 1);
/* Wait for Tx FIFO available */
LPSPI0->TDR = send; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Set TDF flag */
PTD->PTOR |= 1<<0; /* Toggle output on port D0 (blue LED) */
}

Please note that S32K config tool does not support polling method. How to configure the polling method and handle this please?

Re: lpSPI0 Configuration using polling method - S32K144-Q100

danielmartynek — Wed, 05 Apr 2023 09:36:01 GMT

Hi @SivakumarMariappan,

Read LPSPI_SR[TDF]

Read LPSPI_SR[TCF]

Not while(TDF == 1) but while(TDF == 0)

while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);

The TDF flag cannot be set this way:

LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Set TDF flag */

It is set automatically when the number of words in the TX FIFO is < TXWATER

There is S32K144_Project_LPSPI in S32DS IDE rev.2.2

Regards,

Daniel

S32KのトピックlpSPI0 Configuration using polling method - S32K144-Q100

lpSPI0 Configuration using polling method - S32K144-Q100

Re: lpSPI0 Configuration using polling method - S32K144-Q100