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    <title>S32KのトピックRe: PLL calculation for S32k312</title>
    <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617192#M21440</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Didn't fully understand your question, do you mean which divider values can be changed?&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1679014916370.png" style="width: 684px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/215070iAA9BCD506B2860D7/image-dimensions/684x159?v=v2" width="684" height="159" role="button" title="Senlent_0-1679014916370.png" alt="Senlent_0-1679014916370.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;these parameters in the picture can be changed, you can view these clock tree configuration in S32 DS.&lt;/P&gt;</description>
    <pubDate>Fri, 17 Mar 2023 01:06:36 GMT</pubDate>
    <dc:creator>Senlent</dc:creator>
    <dc:date>2023-03-17T01:06:36Z</dc:date>
    <item>
      <title>PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616306#M21410</link>
      <description>&lt;P&gt;hello team,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am using the S32K312 microchip in our design. can please help me to calculate the PLL output frequency. We are using 40 MHz external crystal oscillator. can you provide one example calculation? is it okay if you we are using 40 MHz crystal oscillator?&amp;nbsp;&lt;/P&gt;&lt;P&gt;please provide the clock calculator for&amp;nbsp;S32K312.&lt;/P&gt;</description>
      <pubDate>Thu, 16 Mar 2023 04:41:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616306#M21410</guid>
      <dc:creator>mogilipuri_harish</dc:creator>
      <dc:date>2023-03-16T04:41:13Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616430#M21417</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@mogilipuri_harish" target="_blank"&gt;Hi@mogilipuri_harish&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;The FXOSC can be from 8MHz to40MHz,so the 40MHz crystal oscillator should be ok.&lt;/P&gt;
&lt;P&gt;you can use "S32 Design Studio for S32 Platform" to set the clock tree.&lt;/P&gt;
&lt;P&gt;for example:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1678946272283.png" style="width: 622px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/214855iE6F83FE98C754D30/image-dimensions/622x406?v=v2" width="622" height="406" role="button" title="Senlent_0-1678946272283.png" alt="Senlent_0-1678946272283.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;PS:The S32K312EVB we provide uses a 16MHz external crystal oscillator&lt;/P&gt;</description>
      <pubDate>Thu, 16 Mar 2023 06:02:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616430#M21417</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-03-16T06:02:13Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616484#M21419</link>
      <description>&lt;P&gt;hello senlent,&lt;/P&gt;&lt;P&gt;actually core clock frequency for S32k312 is 120Mhz.&lt;/P&gt;</description>
      <pubDate>Thu, 16 Mar 2023 06:59:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616484#M21419</guid>
      <dc:creator>mogilipuri_harish</dc:creator>
      <dc:date>2023-03-16T06:59:15Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616501#M21420</link>
      <description>&lt;P&gt;thanks for reminding&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In S32K312, CORE_CLK=160Mhz can still run, but it is not recommended for customers to use this way, there will be unknown risks&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 16 Mar 2023 07:13:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616501#M21420</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-03-16T07:13:01Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616649#M21427</link>
      <description>&lt;P&gt;here what are the variable values we can change??&lt;/P&gt;</description>
      <pubDate>Thu, 16 Mar 2023 10:00:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1616649#M21427</guid>
      <dc:creator>mogilipuri_harish</dc:creator>
      <dc:date>2023-03-16T10:00:05Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617192#M21440</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Didn't fully understand your question, do you mean which divider values can be changed?&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1679014916370.png" style="width: 684px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/215070iAA9BCD506B2860D7/image-dimensions/684x159?v=v2" width="684" height="159" role="button" title="Senlent_0-1679014916370.png" alt="Senlent_0-1679014916370.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;these parameters in the picture can be changed, you can view these clock tree configuration in S32 DS.&lt;/P&gt;</description>
      <pubDate>Fri, 17 Mar 2023 01:06:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617192#M21440</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-03-17T01:06:36Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617388#M21449</link>
      <description>&lt;P&gt;hi&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Fxosc = &lt;STRONG&gt;16MHz&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;PLL = (16/2)*60=480MHz&lt;/P&gt;&lt;P&gt;POSTDIV = 480/2 = 240MHz&lt;/P&gt;&lt;P&gt;PHIO = 240MHz/2 = 120MHz&lt;/P&gt;&lt;P&gt;CORE CLK = 120MHz/1=120MHz.&lt;/P&gt;&lt;P&gt;Can you please verify the PLL calculation for 120MHz?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 17 Mar 2023 07:01:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617388#M21449</guid>
      <dc:creator>mogilipuri_harish</dc:creator>
      <dc:date>2023-03-17T07:01:19Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617517#M21458</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;for your reference,for example:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1679045256458.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/215146iCE9199EAA43467F2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Senlent_0-1679045256458.png" alt="Senlent_0-1679045256458.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;PLL output frequency must be in range:640MHz~1,28GHz.&lt;/P&gt;</description>
      <pubDate>Fri, 17 Mar 2023 09:30:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617517#M21458</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-03-17T09:30:07Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617571#M21462</link>
      <description>&lt;P&gt;hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am trying do this PLL clock calculation. can you given some notes how to do this calculation? like reference document. and i didn't find S32k312 example in tools, can you please share that it will be helpful to me.&lt;/P&gt;</description>
      <pubDate>Fri, 17 Mar 2023 10:39:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1617571#M21462</guid>
      <dc:creator>mogilipuri_harish</dc:creator>
      <dc:date>2023-03-17T10:39:25Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1618026#M21478</link>
      <description>&lt;P&gt;Hi@&lt;SPAN&gt;mogilipuri_hari&lt;/SPAN&gt;&lt;WBR /&gt;&lt;SPAN&gt;sh&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Apart from the data sheet, there is no more guidance document for clock configuration&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;As shown in the figure,the version RTD 2.0.1 and above have routines for S32K312&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1679275360762.png" style="width: 590px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/215281iBCD8756FE1BDDFDE/image-dimensions/590x310?v=v2" width="590" height="310" role="button" title="Senlent_0-1679275360762.png" alt="Senlent_0-1679275360762.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Mar 2023 01:25:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/1618026#M21478</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-03-20T01:25:21Z</dc:date>
    </item>
    <item>
      <title>Re: PLL calculation for S32k312</title>
      <link>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/2202692#M54367</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/213282"&gt;@mogilipuri_harish&lt;/a&gt; , were you able to resolve this issue. i am also dealing with same issue. i do have exactly same configuration , using MCAL 6.0.0 for S32K312.&lt;BR /&gt;facing error with "PLL ODIV2 = 2 " out of range</description>
      <pubDate>Tue, 11 Nov 2025 10:37:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/PLL-calculation-for-S32k312/m-p/2202692#M54367</guid>
      <dc:creator>rekhak</dc:creator>
      <dc:date>2025-11-11T10:37:38Z</dc:date>
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