S32KのトピックAbout Time Quanta and SSP offset

About Time Quanta and SSP offset

kimjunghyun — Mon, 27 Mar 2017 10:10:05 GMT

Hi.

I have been developping CAN FD related item.

And I have to check Time Quanta and SSP(secondary sample point) offset.

So please someone helps me.

1. Time Quanta

- at CAN FD frame, Time Quanta in Arbitration phase and Data phase are 5 ~ 48 TQ range. right?

2. How to check SSP offset value?

- at debuging window, there is not any value.

Thank you.

Kim

Re: About Time Quanta and SSP offset

PetrS — Wed, 29 Mar 2017 06:26:36 GMT

Hi Kim,

The bit time during an Arbitration phase is defined by CTRL1 or CBT register.

Note the CBT must be used when CAN FD feature is enabled.

Then the length of bit can have below time quantas.

The bit time for the Data phase is defined by FDCBT register, as below, if the bit rate switching is enabled for CAN FD frame (FDCTRL[FDRATE]=1 and the BRS bit of the Tx MBs is set). Otherwise CTRL1 or CBT registers control bit time of Data phase.

The position of the secondary sample point is defined by the measured loop delay time added to an offset value specified in CAN_FDCTRL[TDCOFF]. CAN_FDCTRL[TDCVAL] bit field stores the result of this calculation.

The TDC mechanism can be enabled by the CAN_FDCTRL[TDCEN] bit and is effectiveonly during the data phase of FD frames having the BRS bit set. It has no effect either on non-FD frames, or on FD frames transmitted at normal bit rate.

BR, Petr

Re: About Time Quanta and SSP offset

kimjunghyun — Wed, 19 Apr 2017 06:58:59 GMT

Hi. Petr.

Thank you for your answer.

For question 1, Time quanta, I understood as below.

- CAN FD arbitration phase : using CAN_CBT

- CAN FD data phase : using CAN_FDCBT

For question 2, How to check SSP offset value, I understood your explanation.

But I could not confirm that the bit of TDCEN and TDCOFF was changed.

- I changed the bit of TDCEN and TDCOFF at the EmbSys Registers but these bits were not changed.

- So I changed these bits at the source code, but I was not sure that these bits were changed.

Because these bits at the EmbSys Registers were changed(1) during RUN but were returned to initial value(0) during SUSPEND.

How can I change the bit of TDCEN and TDCOFF and confirm whether changed or not?

Should I think these bit as changed?

■ At the EmbSys Registers :

1. I changed TDCEN bit to 1

2. but this bit was not changed (the bit was returned to initial value 0, TDC is disabled)

■ At the source code :

1. I changed TDCEN bit to 1

< Before code change >

< After code change : from x to 1 >

2. and TDCEN bit was changed (enabled) during RUN.

3. but TDCEN bit was returned to initial value (disabled) during SUSPEND

Thank you

Kim.