https://community.nxp.com/t5/S32K/S32K342-Memory-mapping/m-p/1597464#M20593 <P>Some information you may find in RM, beginning of Chapter 20 Embedded Flash Memory (c40asf). Also glossary at the end of this chapter.</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_0-1676044575987.png" style="width: 669px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/210511iD2279B24C3B6EACA/image-dimensions/669x400?v=v2" width="669" height="400" role="button" title="davidtosenovjan_0-1676044575987.png" alt="davidtosenovjan_0-1676044575987.png" /></span></P> <P>A documentation to the RTD also contains information about flash organization:</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_1-1676044697352.png" style="width: 667px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/210512i1FEAD4738672EB40/image-dimensions/667x749?v=v2" width="667" height="749" role="button" title="davidtosenovjan_1-1676044697352.png" alt="davidtosenovjan_1-1676044697352.png" /></span></P> <P>If this does not help, please clarify what is needed to explain and I will investigate it further.</P> Fri, 10 Feb 2023 16:01:32 GMT davidtosenovjan 2023-02-10T16:01:32Z https://community.nxp.com/t5/S32K/S32K342-Memory-mapping/m-p/1594542#M20479 <P>Hello NXP Team,</P><P>We are working with S32K342 controller, currently we are stuck in using the memory address/range to suite our requirement wrt placement of our application, bootloader or any user specific block along with memory operation (FLS and FEE modules) accordingly. While referring to the controller user manual it refers to the memory map attachment sheet but couldn't get more details on how internally memory is segregated into sectors. How each sector can be accessible like any reserved sectors/ read only sectors or read write accessible sectors along with size definition.</P><P>Could you please provide the reference for the same. so that it will be more helpful for our task.</P><P>Thank you.</P> Tue, 07 Feb 2023 08:56:51 GMT https://community.nxp.com/t5/S32K/S32K342-Memory-mapping/m-p/1594542#M20479 indumathi_HCL 2023-02-07T08:56:51Z https://community.nxp.com/t5/S32K/S32K342-Memory-mapping/m-p/1597464#M20593 <P>Some information you may find in RM, beginning of Chapter 20 Embedded Flash Memory (c40asf). Also glossary at the end of this chapter.</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_0-1676044575987.png" style="width: 669px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/210511iD2279B24C3B6EACA/image-dimensions/669x400?v=v2" width="669" height="400" role="button" title="davidtosenovjan_0-1676044575987.png" alt="davidtosenovjan_0-1676044575987.png" /></span></P> <P>A documentation to the RTD also contains information about flash organization:</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_1-1676044697352.png" style="width: 667px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/210512i1FEAD4738672EB40/image-dimensions/667x749?v=v2" width="667" height="749" role="button" title="davidtosenovjan_1-1676044697352.png" alt="davidtosenovjan_1-1676044697352.png" /></span></P> <P>If this does not help, please clarify what is needed to explain and I will investigate it further.</P> Fri, 10 Feb 2023 16:01:32 GMT https://community.nxp.com/t5/S32K/S32K342-Memory-mapping/m-p/1597464#M20593 davidtosenovjan 2023-02-10T16:01:32Z