<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: internal clock deviation in S32K</title>
    <link>https://community.nxp.com/t5/S32K/internal-clock-deviation/m-p/1591074#M20330</link>
    <description>&lt;P&gt;&lt;A href="mailto:Hi@yangaichimantou" target="_blank"&gt;Hi@yangaichimantou&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;yes ,you can calculate it like this, but it's not entirely accurate.&lt;/P&gt;
&lt;P&gt;because the PLL has a filtering effect on the input source jitter, there is inherent PLL jitter on the generated output,so a completely accurate calculation is not easy to quantify.&lt;/P&gt;
&lt;P&gt;BR!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 01 Feb 2023 07:32:16 GMT</pubDate>
    <dc:creator>Senlent</dc:creator>
    <dc:date>2023-02-01T07:32:16Z</dc:date>
    <item>
      <title>internal clock deviation</title>
      <link>https://community.nxp.com/t5/S32K/internal-clock-deviation/m-p/1590954#M20326</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We need S32K to calculate high precision time.&lt;/P&gt;&lt;P&gt;We want to know, if we use external crystal of 16M and frequency tolerance of 1 ppm.&lt;/P&gt;&lt;P&gt;S32K internal clock double 10x frequency by PLL.&lt;/P&gt;&lt;P&gt;Then the internal time deviation may be 10 times of the external crystal deviation?&lt;/P&gt;&lt;P&gt;Or do we have other experiment data or calculate method?&lt;/P&gt;</description>
      <pubDate>Wed, 01 Feb 2023 03:44:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/internal-clock-deviation/m-p/1590954#M20326</guid>
      <dc:creator>yangaichimantou</dc:creator>
      <dc:date>2023-02-01T03:44:18Z</dc:date>
    </item>
    <item>
      <title>Re: internal clock deviation</title>
      <link>https://community.nxp.com/t5/S32K/internal-clock-deviation/m-p/1591074#M20330</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@yangaichimantou" target="_blank"&gt;Hi@yangaichimantou&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;yes ,you can calculate it like this, but it's not entirely accurate.&lt;/P&gt;
&lt;P&gt;because the PLL has a filtering effect on the input source jitter, there is inherent PLL jitter on the generated output,so a completely accurate calculation is not easy to quantify.&lt;/P&gt;
&lt;P&gt;BR!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 01 Feb 2023 07:32:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/internal-clock-deviation/m-p/1591074#M20330</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2023-02-01T07:32:16Z</dc:date>
    </item>
  </channel>
</rss>

