topic Re: S32K144 and SBC(MC33FS6500) SPI CS Problem in S32K

S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Mon, 30 Jan 2023 07:36:22 GMT

Hi folks,

When communicating SPI between S32k144 and SBC (MC33FS6500), I see that the Chip Select pin is unexpectedly pulled to high while the message transmission is still in progress.
What can I do ?

My SPI config

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Mon, 30 Jan 2023 10:07:45 GMT

Hi @engineer_attila,

How long the transfer should be?

Can you show how you call the transfer function?

You could increase the .bitcount to 32, for example.

Regards,

Daniel

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Tue, 31 Jan 2023 11:57:07 GMT

Hi @danielmartynek ,

As you seen, 16 clock cycle ,16 bit

This is transfer function

I changed the bitcount to 32, nothing changed.

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Wed, 01 Feb 2023 11:21:34 GMT

Did you really change the bitcount in the configuration of the driver?

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Wed, 01 Feb 2023 13:00:07 GMT

Hi @danielmartynek ,

Our main problem is related to CS pin state inconsistency .

We have to use 16 bit frame format in order to communicate our sensor(FS65xx) . But Sometimes CS pin logic level changed without any reason(as you seen above pictures).

What cause this problem? How can we eliminate this CS select inconsistency

Best regards.

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Wed, 01 Feb 2023 13:09:46 GMT

Hello @engineer_attila,

I'm sorry, I misread the issue.

In this case, can you measure the bus with an analog oscilloscope?

This digital signal does not tell whether the signal goes all the way to VDD or if it is just a glitch.

Does it happen always at the time MOSI is HIGH?

Thanks,

Daniel

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Fri, 03 Feb 2023 06:55:33 GMT

Hi @danielmartynek ,

Most of the times it occurs during when MOSI was HIGH,

But sometimes this CS problem not seen alongs with transmission.

I'm curious , is it related to MOSI?

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Fri, 03 Feb 2023 12:33:24 GMT

Hi @engineer_attila,

Which pin do you use for the CS?

If the pin has the High-drive capability (GPIO-HD), is the the PCR[DSE] bit of the pin set?

Thanks,

BR, Daniel

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Fri, 03 Feb 2023 15:11:32 GMT

Hi @danielmartynek ,

This is my pin configuration

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Mon, 06 Feb 2023 11:17:59 GMT

This PTB17 does not have the GPIO-HD function.

Can you use different PCS?

Like PTB5

Have you been able to measure the signal with an analog osciloscope?

Can you decrease the bitrate?

Thanks,

BR, Daniel

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

engineer_attila — Fri, 17 Feb 2023 08:35:10 GMT

Hi @danielmartynek ,

Sorry for late response. My colleagues will change the CS pin to GPIO-HD for next revision.

I'm curious what is the equivalent of GPIO-HD pins for MPC5775 series?

Best regards.

Re: S32K144 and SBC(MC33FS6500) SPI CS Problem

danielmartynek — Fri, 17 Feb 2023 11:33:08 GMT

Hello @engineer_attila,

Did you get rid of the glitches with this configuration? How does it look at an analog osciloscope?

I'm not familiar with the MPC5775 series, but I see there is a similar option in the PCR[SRC] register.

On S32K1xx, the GPIO-HD pins with PCR[DSE] = 1 have higher current capabilities and are faster.

Also, the whole LPSPI specification in the DS was taken at GPIO-HD pins (DSE = 1):

Regards,

Daniel