<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Ask whether csec is enabled in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Ask-whether-csec-is-enabled/m-p/1575910#M19728</link>
    <description>&lt;P&gt;I have a chip of model s32k148, but I do not know that the chip enables CSEc function. If the CSEc function is enabled, I fear that the chip will be locked after mass erass are executed. So please ask if there are any methods to determine whether my chip enables CSEc function. If it can be determined, can the number of CSEc keys set be read?&lt;/P&gt;</description>
    <pubDate>Sun, 01 Jan 2023 07:47:52 GMT</pubDate>
    <dc:creator>yangyong6479</dc:creator>
    <dc:date>2023-01-01T07:47:52Z</dc:date>
    <item>
      <title>Ask whether csec is enabled</title>
      <link>https://community.nxp.com/t5/S32K/Ask-whether-csec-is-enabled/m-p/1575910#M19728</link>
      <description>&lt;P&gt;I have a chip of model s32k148, but I do not know that the chip enables CSEc function. If the CSEc function is enabled, I fear that the chip will be locked after mass erass are executed. So please ask if there are any methods to determine whether my chip enables CSEc function. If it can be determined, can the number of CSEc keys set be read?&lt;/P&gt;</description>
      <pubDate>Sun, 01 Jan 2023 07:47:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Ask-whether-csec-is-enabled/m-p/1575910#M19728</guid>
      <dc:creator>yangyong6479</dc:creator>
      <dc:date>2023-01-01T07:47:52Z</dc:date>
    </item>
  </channel>
</rss>

