topic Re: Flexcan, before send data, status the RAMn4 and RAMn5 in S32K

Flexcan, before send data, status the RAMn4 and RAMn5

buccno — Thu, 22 Dec 2022 08:13:55 GMT

Hi,
I wonder why this change happens.

Re: Flexcan, before send data, status the RAMn4 and RAMn5

buccno — Thu, 22 Dec 2022 09:08:06 GMT

I'm confused about one more thing, For example, I have a 64-bit length message with a single ID. how can I get bit 4.(starter bit),(length 4 bit), and bit (starter bit)50.(length 4 bit)?

Re: Flexcan, before send data, status the RAMn4 and RAMn5

Senlent — Fri, 23 Dec 2022 06:59:20 GMT

Hi@buccno

Q1.you can take a look at the S32-RM Chapter 55.4.3 Message buffer structure-

>CODE->Message Buffer Code,

Both receiving and sending will query and update the CODE area.

Q2.You mean to parse a frame of data, which can be achieved by a shift operation, for example:

bit1~3 = (recvBuff.data[0] >> 1) & 0x07;;