S32KのトピックRe: S32K344 ADC data alignment and bit resolution

S32K344 ADC data alignment and bit resolution

kyf — Fri, 16 Dec 2022 13:15:23 GMT

Hello NXP team!

I need to know what happens regarding the data alignment of the ADC. I have done some tests and I've seen that in order to get the adc data from the regirster I have to consider the alignment AND the bit resolution in order to do the correct mask+shifting in order to get the data.

I've also noticed that if I set the resolution to 8 bit I get some data in the non-significant bits that are probably rubbish and they are not related to the ADC data.

I'm putting an image bellow that shows the adc data alignment in regard with the bit resolution at the PCDR0->CDATA register and at the FIFO1DR->ADC_DATA. I've noticed that the value in those registers are the same.

kyf_0-1671195146745.png

1. Is the above image correct ?

With resolution 8 bits and right alignment i was expecting to see this:

kyf_1-1671195254078.png

but instead I've seen this when I debugged the registers:

kyf_2-1671195343743.png

2. Are the ADC data being readden by making and shifting the registers data ?

3. Which is the correct format that the data are stored inside the registers ? I would like not to use the CPU in order to shift or mask the data because that would render the whole timerTrigg->Bctu->Dma transfer pointless if I have to use the CPU for such a reason.

I've read the ADC, BCU and the AN13413 but I didn't understand how the registers store the ADC data. Bellow are some parts regarding the alignment and the resolution.

kyf_3-1671195664002.png

kyf_0-1671195754602.png

kyf_1-1671196020845.png

Here it seems that the data are shifted according to the selected resolution.

A. This is the code regarding reading data from the ADC

kyf_2-1671196141486.pngkyf_3-1671196218485.png

B. This is the code regarding reading data from the FIFO1 of the BCTU

kyf_4-1671196346044.pngkyf_5-1671196362453.png

4. How should I handle the data if my assumptions are correct ?

I have to port code and the data are stored in a buffer array with DMA. Should I use right alignment and shift the data before used in the code ? is there anything else that I could try ?

Kind regards,

kyf

Re: S32K344 ADC data alignment and bit resolution

kyf — Fri, 16 Dec 2022 13:40:12 GMT

Here is a screenshot from the registers after a BCTU/Adc measurement.

The bellow image shows a RightAligned data with 8bit resolution.

kyf_0-1671197874093.png

My main query is: Where are my data stored ? Is my data stored at bit 13-6 ?? or are they somewhere else ?

Re: S32K344 ADC data alignment and bit resolution

davidtosenovjan — Tue, 20 Dec 2022 16:41:35 GMT

It is expected. Result is displayed always with maximum resolution. In case resolution is smaller, then LSB bits are cut (considering right align). With left align it is the same, but from left side.

Re: S32K344 ADC data alignment and bit resolution

kyf — Wed, 21 Dec 2022 08:24:33 GMT

Hello @davidtosenovjan . Thank you for your reply.

The thing is that when I'm selecting right align the LSB are not cut. For example:

My settings are 12bits resolution + right aligned. After the ADC conversion the MSB (11th bit) of the result is located at bit 13 of the register like the image bellow and not at bit 11 of the register as the alignment settings suggest.

kyf_0-1671610562408.png

and in order to get the adc data I have to shift them right 3 times in the firmware.

Am I missing something ? Shouldn't the LSB be at bit 0 when I select right alignment settings ?

Kind regards,

kyf

Re: S32K344 ADC data alignment and bit resolution

davidtosenovjan — Wed, 21 Dec 2022 14:37:44 GMT

Or you may see it otherwise.

RM says that data in the result registers are always 15-bit (although I am not sure why it is stated because user cannot choose 15-bit resolution, only 14-bit)
Right-aligned data occupies *CDR[14:0],
Left-aligned data occupies *CDR[15:1].

For right aligned and
14 bit - 0 bits disappear from right
12 bit - 2 bits disappear from right
8 bit - 6 bits disappear from right

For left aligned and
14 bit - 2 bits (i.e. 16-14) disappear from right
12 bit - 4 bits disappear from right
8 bit - 8 bits disappear from right

If you application cannot use it in this format, you will have to perform shifts SW way or use different alignment.