S32KのトピックRe: S32K344 ADC: HAS_ADC_INTERLEAVE problem

S32K344 ADC: HAS_ADC_INTERLEAVE problem

Du_0224 — Fri, 04 Nov 2022 11:06:57 GMT

Dear NXP engineer, Hello.
I am debugging the ADC function of S32K344_EVB, development environment: EBtresos 28.2.0+S32DS

I want to use PIN_PTA1 as ADC0_S9 function, but I found that the acquisition ADC failed. Then I found that DCM.DCMRWF4[2] is set to 1 by MCAL program by default.

Du_0224_4-1667559762846.png

Du_0224_1-1667558362031.png

Du_0224_2-1667558418035.png

MCAL static code library: SIUL2_PORT_IP_HAS_ADC_INTERLEAVE is defined by default.
The logic in the static code：
PORT_WRITE32(DCM_DCMRWF4_ADDR32, DCM_DCMRWF4_ADC_INTERLEAVE_MASK | dcmrwf4RegValue);

0x0000067E | 0x0000067A = 0x0000067E ? (DCMRWF4.MUX_MODE_EN_ADC0_S9 = 1(is PTB14))

will enable all ADC INTERLEAVE in DCMRWF4 to 1.
What is the purpose of this logic, as the manual should all be set to 0 by default.
Shouldn't this logic be changed to something like the following：
PORT_WRITE32(DCM_DCMRWF4_ADDR32, DCM_DCMRWF4_ADC_INTERLEAVE_MASK & dcmrwf4RegValue);

0x0000067E & 0x0000067A = 0x0000067A (DCMRWF4.MUX_MODE_EN_ADC0_S9 = 0(is PTA1))

Du_0224_3-1667558620062.png

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Re: S32K344 ADC: HAS_ADC_INTERLEAVE problem

Du_0224 — Fri, 04 Nov 2022 11:12:30 GMT

Attached is the PIN_PTA1 pin configuration for MCAL.

Du_0224_0-1667560345807.png

Re: S32K344 ADC: HAS_ADC_INTERLEAVE problem

Robin_Shen — Mon, 07 Nov 2022 02:28:33 GMT

Hi Du_0224,

Thank you for the report.
And sorry for the inconvenience we bring you!
The problem of Siul2_Port_Ip_WriteDCMConfiguration has been reported to the RTD team before, but the fix version has not been released yet, so the customer needs to manually modify it temporarily.

You can see this similar discussion: S32K3_ADC_Channcal_configure_problem

Best Regards,
Robin
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Re: S32K344 ADC: HAS_ADC_INTERLEAVE problem

Du_0224 — Mon, 07 Nov 2022 02:43:37 GMT

Hi Robin,

Thank you for your reply.
I have been able to use ADC properly by changing RTD_LLD manually.
I will follow up with RTD updates.