S32KのトピックRe: S32K144 spi

S32K144 spi

yinzc — Sun, 09 Oct 2022 10:18:21 GMT

Hi，what the maximum data length transmitted at one time?I try to transmit 72 bits but only 32 bits transmitted.

Re: S32K144 spi

Senlent — Mon, 10 Oct 2022 02:53:19 GMT

The TX FIFO for each spi instance has 4 words, one word size = 32 bits. The length of TDR is 32 bits, and the data written to the FIFO is 32 bits each time.（TDR:Transmit Data Register）.

Re: S32K144 spi

yinzc — Mon, 10 Oct 2022 07:30:51 GMT

Hi，Senlent.

Thank you for your reply,how to write register if i want to transmit a 72 bits data?

Re: S32K144 spi

Senlent — Mon, 10 Oct 2022 08:04:53 GMT

Hi@yinzc

Can you tell me which IDE and library you are using? or you can send me your demo code.

Re: S32K144 spi

yinzc — Mon, 10 Oct 2022 08:23:48 GMT

Hello, i'm using S32 Design Studio for ARM Version 2018.R1 and the demo is 'LPSPI_s32k144'.

Please see the following pic.

Re: S32K144 spi

Senlent — Mon, 10 Oct 2022 08:41:24 GMT

thank you, and I need some time to finish this demo.

Re: S32K144 spi

yinzc — Tue, 11 Oct 2022 01:33:20 GMT

Thanks.

I'm looking forward to your reply.

Re: S32K144 spi

Senlent — Tue, 11 Oct 2022 06:40:20 GMT

Hi@yinzc

3.the blue one is LPSPI1_PCS3 and the yellow one is LPSPI1_SOUT.

note,here i did not observe the waveform of LPSPI1_SIN,because there is no slave device on my side,so i am not sure what i configured is correct,you can test is with your slave device.

Re: S32K144 spi

yinzc — Tue, 11 Oct 2022 09:58:25 GMT

Thanks Senlent，It helps me a lot.

Re: S32K144 spi

yinzc — Fri, 14 Oct 2022 06:50:41 GMT

Hi,i am trying to send 40bits data whitch is 25ms cyclic.

The first group of data is shown followin

The second group of data is shown followin

The third group of data is shown followin\

The first two groups are both normal. The third group is a little abnormal. After the third group sends, both the chip selection and the clock are pulled down. They should be pulled up normally and no data is sent after three times.

Can you help me solve this problem？

Best regards

Thanks

Re: S32K144 spi

Senlent — Fri, 14 Oct 2022 07:11:19 GMT

你自己先找下原因，监控下Status Register (SR) 看看有什么异常，不接slave device会不会这样，可以改一下我提供的示例代码，将收发单独分开来（先都发完再读FIFO），然后再测一下，还有会不会是slave device的特性，自己拉低了总线，

Re: S32K144 spi

yinzc — Fri, 14 Oct 2022 09:05:24 GMT

你好，是SR寄存器的MBF置位了，我现在用的是SPI1,我用相同的配置配置SPI0,数据能正常循环发送，请问这是什么原因呢

Re: S32K144 spi

Senlent — Fri, 14 Oct 2022 09:35:05 GMT

会不会你的两个模块的设置上存在差异，SR的其它只有MBF异常吗？FIFO overflow可能也会导致MBF异常，速度再降一下，你先排查一下吧，下周问题没头绪，再讨论吧