<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32K324 memory insufficient issue in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K324-memory-insufficient-issue/m-p/1521953#M17705</link>
    <description>&lt;P&gt;If I understand your questions correctly, you would like to use SRAM address space that is by default allocated to Core 1 by Core 0.&lt;/P&gt;
&lt;P&gt;MCU allows such accesses, as there are only different XBAR slaves for these SRAM controllers, but it is accessible by both cores, so I don't see an issue to join these areas together if you don't use Core 1.&lt;/P&gt;</description>
    <pubDate>Wed, 14 Sep 2022 14:56:59 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2022-09-14T14:56:59Z</dc:date>
    <item>
      <title>S32K324 memory insufficient issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-memory-insufficient-issue/m-p/1520477#M17646</link>
      <description>&lt;P&gt;Hi Nxp team,&lt;/P&gt;&lt;P&gt;We use S32K324 &lt;SPAN&gt;with RTD 2.0.0 in S32DS and we only develop M7_0 in&amp;nbsp;our project, but&amp;nbsp;memory size is overflow now. In order to adding memory size, we would like to use&amp;nbsp;M7_1 memory space for&amp;nbsp;M7_0 using. May we use below memory c1(circle in red) for M7_0? Is it workable?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;If it's workable, could you give us some suggestions for memory configuration or provide us sample linkerfile?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="fxn_0-1662976309480.png" style="width: 689px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/193278iACDA243065CACDFE/image-dimensions/689x255?v=v2" width="689" height="255" role="button" title="fxn_0-1662976309480.png" alt="fxn_0-1662976309480.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;fxn_0-1662976309480.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Wade&lt;/P&gt;</description>
      <pubDate>Mon, 12 Sep 2022 10:04:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-memory-insufficient-issue/m-p/1520477#M17646</guid>
      <dc:creator>fxn</dc:creator>
      <dc:date>2022-09-12T10:04:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 memory insufficient issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-memory-insufficient-issue/m-p/1521953#M17705</link>
      <description>&lt;P&gt;If I understand your questions correctly, you would like to use SRAM address space that is by default allocated to Core 1 by Core 0.&lt;/P&gt;
&lt;P&gt;MCU allows such accesses, as there are only different XBAR slaves for these SRAM controllers, but it is accessible by both cores, so I don't see an issue to join these areas together if you don't use Core 1.&lt;/P&gt;</description>
      <pubDate>Wed, 14 Sep 2022 14:56:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-memory-insufficient-issue/m-p/1521953#M17705</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2022-09-14T14:56:59Z</dc:date>
    </item>
  </channel>
</rss>

