FlexIO Timer

JustMet — Thu, 25 Aug 2022 08:45:24 GMT

Hello All,

I am using FLexIO for PWM geneartion and everything is mostly working properly and i am faing error in Transmission as you can see i am using 2 timer for SENT. TImer0 is working properly with no or less red data but for timer 1 its too much red data(if data is different) if i transmit same data then both are smae with less error.

Best regards,
JustMet

/************ SHIFTER Data OUT CONFIGURATION *************************************/
FLEXIO->SHIFTCTL[0] = FLEXIO_SHIFTCTL_SMOD(2) | /* 2: Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer */
FLEXIO_SHIFTCTL_PINPOL(0) | /* 0: Pin is active high */
FLEXIO_SHIFTCTL_PINSEL(0) | /* 1: Select the FXIO_D0 pin */
FLEXIO_SHIFTCTL_PINCFG(0) | /* 0: Shifter pin output disabled */
FLEXIO_SHIFTCTL_TIMPOL(1) | /* 1: Shift on negedge of Shift clock */
FLEXIO_SHIFTCTL_TIMSEL(0); /* 0: Select Timer 0 */

FLEXIO->SHIFTCFG[0] = FLEXIO_SHIFTCFG_SSTART(0) | /* 0: Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable */
FLEXIO_SHIFTCFG_SSTOP(0) | /* 0: Stop bit disabled for transmitter/receiver/match store */
FLEXIO_SHIFTCFG_INSRC(0); /* 0: Pin */

/************* TIMER BitCLK OUT CONFIGURATION *********************************/
/* The Timer Configuration Register (TIMCFGn) should be configured before setting the Timer Mode (TIMOD).*/
FLEXIO->TIMCFG[0] = FLEXIO_TIMCFG_TSTART(0) | /* 0: Start bit disabled */
FLEXIO_TIMCFG_TSTOP(0) | /* 0: Stop bit disabled */
FLEXIO_TIMCFG_TIMENA(2) | /* 2: Timer enabled on Trigger high */
FLEXIO_TIMCFG_TIMDIS(0) | /* 0: Timer never disabled */
FLEXIO_TIMCFG_TIMRST(0) | /* 0: Timer never reset */
FLEXIO_TIMCFG_TIMDEC(0) | /* 0: Decrement counter on FlexIO clock, Shift clock equals Timer output */
FLEXIO_TIMCFG_TIMOUT(2); /* 2: Timer output is logic one when enabled and on timer reset */

FLEXIO->TIMCTL[0] = FLEXIO_TIMCTL_TIMOD(2) | /* 2: Dual 8-bit counters PWM mode */
FLEXIO_TIMCTL_PINPOL(0) | /* 0: Pin is active high */
FLEXIO_TIMCTL_PINSEL(1) | /* 1: Select the FXIO_D1 pin */
FLEXIO_TIMCTL_PINCFG(3) | /* 3: Timer pin output */
FLEXIO_TIMCTL_TRGSRC(1) | /* 1: Internal trigger selected */
FLEXIO_TIMCTL_TRGPOL(1) | /* 1: Trigger active low */
FLEXIO_TIMCTL_TRGSEL(1); /* 1: 4*N+1 - Shifter N(0) status flag */

/************ SHIFTER Data OUT CONFIGURATION *************************************/
FLEXIO->SHIFTCTL[1] = FLEXIO_SHIFTCTL_SMOD(2) | /* 2: Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer */
FLEXIO_SHIFTCTL_PINPOL(0) | /* 0: Pin is active high */
FLEXIO_SHIFTCTL_PINSEL(2) | /* 1: Select the FXIO_D2 pin */
FLEXIO_SHIFTCTL_PINCFG(0) | /* 0: Shifter pin output disabled */
FLEXIO_SHIFTCTL_TIMPOL(1) | /* 1: Shift on negedge of Shift clock */
FLEXIO_SHIFTCTL_TIMSEL(1); /* 0: Select Timer 1 */

FLEXIO->SHIFTCFG[1] = FLEXIO_SHIFTCFG_SSTART(0) | /* 0: Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable */
FLEXIO_SHIFTCFG_SSTOP(0) | /* 0: Stop bit disabled for transmitter/receiver/match store */
FLEXIO_SHIFTCFG_INSRC(0); /* 0: Pin */

/************* TIMER BitCLK OUT CONFIGURATION *********************************/
/* The Timer Configuration Register (TIMCFGn) should be configured before setting the Timer Mode (TIMOD).*/
FLEXIO->TIMCFG[1] = FLEXIO_TIMCFG_TSTART(0) | /* 0: Start bit disabled */
FLEXIO_TIMCFG_TSTOP(0) | /* 0: Stop bit disabled */
FLEXIO_TIMCFG_TIMENA(2) | /* 2: Timer enabled on Trigger high */
FLEXIO_TIMCFG_TIMDIS(0) | /* 0: Timer never disabled */
FLEXIO_TIMCFG_TIMRST(0) | /* 0: Timer never reset */
FLEXIO_TIMCFG_TIMDEC(0) | /* 0: Decrement counter on FlexIO clock, Shift clock equals Timer output */
FLEXIO_TIMCFG_TIMOUT(2); /* 2: Timer output is logic one when enabled and on timer reset */

FLEXIO->TIMCTL[1] = FLEXIO_TIMCTL_TIMOD(2) | /* 2: Dual 8-bit counters PWM mode */
FLEXIO_TIMCTL_PINPOL(0) | /* 0: Pin is active high */
FLEXIO_TIMCTL_PINSEL(4) | /* 1: Select the FXIO_D4 pin */
FLEXIO_TIMCTL_PINCFG(3) | /* 3: Timer pin output */
FLEXIO_TIMCTL_TRGSRC(1) | /* 1: Internal trigger selected */
FLEXIO_TIMCTL_TRGPOL(1) | /* 1: Trigger active low */
FLEXIO_TIMCTL_TRGSEL(5); /* 1: 4*N+1 - Shifter N(0) status flag */

Re: FlexIO Timer

danielmartynek — Mon, 29 Aug 2022 12:44:49 GMT

Hi @JustMet,

If you disable timer 0, does timer 2 work correctly.

An example is attached, can you compare the code?

But the application spends some time in the FlexIO ISR, and it can servise both at the same time.

BR, Daniel

Re: FlexIO Timer

JustMet — Tue, 30 Aug 2022 10:32:15 GMT

Hello Daniel,

No, If I disable timer 0, timer 2 doesn't work correctly.
Yes i am using the similar code i will also attach my main file.

Best regards,
JustMet

Re: FlexIO Timer

danielmartynek — Fri, 02 Sep 2022 13:09:45 GMT

Hello @JustMet,

Sorry for the delay, I have been busy.

I see a few issues in the code.

1. You should have a separate state machine for each of the channels in the ISR, not just one for both.

2. Also, you don't poll and clear the second flag.

3. Don't use read-modify-write (|= operation) to clear the flags. These are W1C bits, you have to use a direct write just to the flag you want to clear.

BR, Daniel

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