https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1498303#M16747 <P>That make sense, thank you for your response.</P> Sat, 30 Jul 2022 20:15:29 GMT Psabouri 2022-07-30T20:15:29Z https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1488429#M16327 <P>Hi,</P><P>I have a S32K344 evaluation board. I am configuring the LPSPI_0 to transfer 16-bit data at 8MHz. The CLK is outputted on PTC8 (standard plus pad).&nbsp; As you can see in the figure below, the CLK periodicity is incorrect and it is changing!!! Why CLK is behaving like this?</P><P>LPSPI_0 functional clock is 80MHz</P><P>CCR1[SCKHLD] = CCR1[SCKSET] = 4</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Psabouri_0-1657681524704.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/186394i0D925EDD7B1147B6/image-size/medium?v=v2&amp;px=400" role="button" title="Psabouri_0-1657681524704.png" alt="Psabouri_0-1657681524704.png" /></span></P><P>When the bus rate is decreased to 5MHz, the CLK behaves correctly.</P> Wed, 13 Jul 2022 03:18:23 GMT https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1488429#M16327 Psabouri 2022-07-13T03:18:23Z https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1489592#M16372 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203591">@Psabouri</a>&nbsp;</P> <P><SPAN>The problem may be in the configuration of your sample rate, y</SPAN><SPAN>ou should increase the sample rate in order to have a better resolution of the clock signal.&nbsp;</SPAN></P> <P>&nbsp;</P> <P>B.R.</P> <P>VaneB</P> Thu, 14 Jul 2022 15:04:25 GMT https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1489592#M16372 VaneB 2022-07-14T15:04:25Z https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1498303#M16747 <P>That make sense, thank you for your response.</P> Sat, 30 Jul 2022 20:15:29 GMT https://community.nxp.com/t5/S32K/LPSPI-CLK/m-p/1498303#M16747 Psabouri 2022-07-30T20:15:29Z